@techreport{Nolte2013, author = {Nolte, J{\"o}rg}, title = {12. GI/ITG Fachgespr{\"a}ch Sensornetze}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-28986}, year = {2013}, abstract = {Drahtlose Sensornetze stellen eine vielversprechende Technologie zur Beobachtung und Beeinflussung von Vorg{\"a}ngen in der realen Welt dar. Autonome Sensorknoten nehmen dabei Parameter der Umwelt durch Sensoren wahr und k{\"o}nnen diese durch Aktoren beeinflussen. Viele solcher autonomen und ressourcenbeschr{\"a}nkten Knoten kooperieren dabei mittels drahtloser Kommunikation. Die Eigenschaften dieser Knoten und Netze implizieren eine Vielzahl von neuartigen Herausforderungen, die sich in einer regen Forschungsaktivit{\"a}t widerspiegeln. Ziel dieser Reihe von Fachgespr{\"a}chen ist es, Wissenschaftlerinnen und Wissenschaftlern aus Hochschule und Industrie die M{\"o}glichkeit zu einem informellen Gedankenaustausch zu geben und die Kooperation in diesem multidisziplin{\"a}ren Forschungsbereich zu verst{\"a}rken.}, subject = {Drahtloses Sensorsystem}, language = {en} } @inproceedings{SegabinazziFerreiraNolte2019, author = {Segabinazzi Ferreira, Raphael and Nolte, J{\"o}rg}, title = {Low latency reconfiguration mechanism for fine-grained processor internal functional units}, doi = {10.1109/LATW.2019.8704560}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-50497}, year = {2019}, abstract = {The strive for performance, low power consumption, and less chip area have been diminishing the reliability and the time to fault occurrences due to wear out of electronic devices. Recent research has shown that functional units within processors usually execute a different amount of operations when running programs. Therefore, these units present different individual wear out during their lifetime. Most existent schemes for re-configuration of processors due to fault detection and other processor parameters are done at the level of cores which is a costly way to achieve redundancy. This paper presents a low latency (approximately 1 clock cycle) software controlled mechanism to reconfigure units within processor cores according to predefined parameters. Such reconfiguration capability delivers features like wear out balance of processor functional units, configuration of units according to the criticality of tasks running on an operating system and configurations to gain in performance (e.g. parallel execution) when possible. The focus of this paper is to show the implemented low latency reconfiguration mechanism and highlight its possible main features.}, subject = {Functional units low latency; Fine-grained; Reconfiguration; Software; Rekonfiguration; Mikroprozessor; Latenzzeit }, language = {en} } @inproceedings{RottaSegabinazziFerreiraNolte2020, author = {Rotta, Randolf and Segabinazzi Ferreira, Raphael and Nolte, J{\"o}rg}, title = {Real-time dynamic hardware reconfiguration for processors with redundant functional units}, series = {Proceedings of the 2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC)}, booktitle = {Proceedings of the 2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC)}, publisher = {Institute of Electrical and Electronics Engineers Inc. (IEEE)}, address = {Nashville, TN, USA}, isbn = {978-1-7281-6958-3}, issn = {2375-5261}, doi = {10.1109/ISORC49007.2020.00035}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-52031}, year = {2020}, abstract = {The tiny logic elements in modern integrated circuits increase the rate of transient failures significantly. Therefore, redundancy on various levels is necessary to retain reliability. However, for mixed-criticality scenarios, the typical processor designs offer either too little fault-tolerance or too much redundancy for one part of the applications. Amongst others, we specifically address redundant processor internal functional units (FU) to cope with transient errors and support wear leveling. A real-time operating system (RTOS) was extended to control our prototypical hardware platform and, since it can be configured deterministically within few clock cycles, we are able to reconfigure the FUs dynamically, at process switching time, according to the specified critically of the running processes. Our mechanisms were integrated into the Plasma processor and the Plasma-RTOS. With few changes to the original software code, it was, for example, possible to quickly change from fault-detecting to fault-correcting modes of the processor on demand.}, subject = {Reconfiguration; Run-Time; Modular redundancy; Mixed-criticality; Rekonfiguration; Laufzeit; Funktionseinheit; Redundanz }, language = {en} } @inproceedings{SegabinazziFerreiraGeorgeChenetal.2019, author = {Segabinazzi Ferreira, Raphael and George, Nevin and Chen, Junchao and H{\"u}bner, Michael and Krstic, Milos and Nolte, J{\"o}rg and Vierhaus, Heinrich Theodor}, title = {Configurable Fault Tolerant Circuits and System Level Integration for Self-Awareness}, isbn = {978-3-902457-54-7}, doi = {10.26127/BTUOpen-5050}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-50503}, year = {2019}, abstract = {Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on-line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system.}, subject = {Self-awareness; Configurable circuits; Fault tolerant; Operation modes; Integrierte Schaltung; Konfiguration ; Fehlertoleranz}, language = {en} } @misc{KurthBachmannHeineretal.2006, author = {Kurth, Winfried and Bachmann, Peter and Heiner, Monika and K{\"o}nig, Hartmut and Kraemer, Rolf and Lewerentz, Claus and Nolte, J{\"o}rg and Thalheim, Bernhard and Vierhaus, Heinrich Theodor and Braunm{\"u}hl, Burchard von and Wagner, Gerd}, title = {Jahresbericht 2003/2005 / Institut fuer Informatik, Informations- und Medientechnik}, organization = {Brandenburgische Technische Universit{\"a}t Cottbus / Institut f{\"u}r Informatik, Informations- und Medientechnik}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-3488}, year = {2006}, abstract = {Selbstdarstellung des Instituts f{\"u}r Informatik, Informations- und Medientechnik der BTU Cottbus und Berichte der Lehrst{\"u}hle f{\"u}r die Jahre 2003, 2004 und 2005.}, subject = {Cottbus / Technische Universit{\"a}t; Bericht; Informatik; Informations- und Medientechnik; BTU Cottbus; Computer Science; Information Technology; Media Technology; BTU Cottbus}, language = {de} } @misc{ThalheimHeinerKurthetal.2003, author = {Thalheim, Bernhard and Heiner, Monika and Kurth, Winfried and Bachmann, Peter and K{\"o}nig, Hartmut and Lewerentz, Claus and Vierhaus, Heinrich Theodor and Braunm{\"u}hl, Burchard von and Nolte, J{\"o}rg}, title = {Jahresbericht 2001/2002 / Institut f{\"u}r Informatik}, organization = {Brandenburgische Technische Universit{\"a}t Cottbus / Institut f{\"u}r Informatik}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-3527}, year = {2003}, abstract = {Selbstdarstellung des Instituts f{\"u}r Informatik der BTU Cottbus und Berichte der Lehrst{\"u}hle f{\"u}r die Jahre 2001 und 2002.}, subject = {Cottbus / Technische Universit{\"a}t; Bericht; Informatik; BTU Cottbus; Computer Science; BTU Cottbus}, language = {de} } @inproceedings{SegabinazziFerreiraNolteVargasetal.2020, author = {Segabinazzi Ferreira, Raphael and Nolte, J{\"o}rg and Vargas, Fabian and George, Nevin and H{\"u}bner, Michael}, title = {Run-time hardware reconfiguration of functional units to support mixed-critical applications}, doi = {10.1109/LATS49555.2020.9093692}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-51804}, year = {2020}, abstract = {System reconfiguration of hardware resources has been done in multiple system domains. Such systems are usually found in the context of FPGAs, where reconfiguration is done usually over its primitives (e.g., LUTs, Flip-Flops). Or even in the context of MPSoC designs, where core management (e.g., lock-step operation in multi-core designs) is the most used approach. However, recent works have shown that configuration at Functional Units (FUs) granularity might come with benefits. For example, it can increase the configuration space due to its finer granularity, and, as a consequence, the options to deal with problems (e.g., due to aging) in the units itself. Within this context, this paper presents a system capable to configure its FUs (e.g., ALUs, multipliers, dividers) into different operation modes. The system uses an Operating System to control HW reconfiguration during process switching time and takes into account the health state of its units in a mixed-criticality applications scenario. Results show that, within this scenario, the system is able to reconfigure itself accomplishing health state modifications of its HW elements.}, subject = {Reconfiguration; Functional units; Fine-grained; Mixed-criticality; Run-time; Rekonfiguration; Laufzeit; Funktionseinheit; Fehlererkennung}, language = {en} } @incollection{BuechnerNolteHasanietal., author = {B{\"u}chner, Steffen and Nolte, J{\"o}rg and Hasani, Alireza and Kraemer, Rolf and Lopacinsiki, Lukasz}, title = {End2End100 : communication protocol processing for ultra high data rates}, series = {Wireless 100 Gbps and beyond : architectures, approaches and findings of German Research Foundation (DFG) Priority Programme SPP1655}, booktitle = {Wireless 100 Gbps and beyond : architectures, approaches and findings of German Research Foundation (DFG) Priority Programme SPP1655}, doi = {10.26127/BTUOpen-5916}, publisher = {BTU Cottbus - Senftenberg}, pages = {359 -- 396}, abstract = {In 2012 a group of researchers proposed a basic research initiative to the German Research Foundation (DFG) as a special priority project (SPP) with the name: Wireless 100 Gbps and beyond. The main goal of this initiative was the investigation of architectures, technologies and methods to go well beyond the state of the art. The target of 100 Gbps was set far away from the (at that time) achievable 1 Gbps such that it was not possible to achieve promising results just by tuning some parameters. We wanted to find breakthrough solutions. When we started the work on the proposal we discussed the challenges to be addressed in order to advancing the wireless communication speed significantly. Having the fundamental Shannon boundary in mind we discussed how to achieve the 100 Gbps speed.}, subject = {100 Gbps; Wireless; Drahtlos; End2End100; Communication protocol processing; Kommunikations-Protokoll-Prozessierung; Drahtloses Sensorsystem; Hochfrequenztechnik; Antenne; Terahertzbereich; Energieffizienz}, language = {en} }