@phdthesis{Veleski2022, author = {Veleski, Mitko}, title = {A cross-layer framework for adaptive processor-based systems regarding error resilience and power efficiency}, doi = {10.26127/BTUOpen-6145}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-61450}, school = {BTU Cottbus - Senftenberg}, year = {2022}, abstract = {This dissertation proposes a cross-layer framework able to synergistically optimize resilience and power consumption of processor-based systems. It is composed of three building blocks: SWIELD multimodal flip-flop (FF), System Operation Management Unit (SOMU) and Framework Function Library (FFL). Implementation of the building blocks is performed at circuit, architecture and software layer of the system stack respectively. The SWIELD FF can be configured to operate as a regular flip-flop or as an enhanced flip-flop for protection against timing/radiation-induced faults. It is necessary to perform replacement of selected timing-critical flip-flops in a system with SWIELD FFs during design time. When the system is active, the SWIELD FFs operation mode is dynamically managed by the SOMU controller according to the current requirements. Finally, the FFL contains a set of software procedures that greatly simplify framework utilization. By relying on the framework, a system can intelligently interchange techniques such as Adaptive Voltage/Frequency Scaling, selective Triple Modular Redundancy and clock gating during operation. Additionally, a simple and convenient strategy for integration of the framework in processor-based systems is also presented. A key feature of the proposed strategy is to determine the number of SWIELD FFs to be inserted in a system. Using this strategy, the framework was successfully embedded in instances of both single- and multicore systems. Various experiments were conducted to evaluate the framework influence on the target systems with respect to resilience and power consumption. At expense of about 1\% area overhead, the framework is able to preserve performance and to reduce power consumption up to 15\%, depending on the number of SWIELD FFs in the system. Furthermore, it was also shown that under certain conditions, the framework can provide failure-free system operation.}, subject = {Processor; Cross-layer; Power; Resilience; Prozessoren; Energieeffizienz; Leistungseffizienz; Fehlerresilienz; Prozessor; Modell; Energieeffizienz; Fehlertoleranz}, language = {en} }