@phdthesis{KalishettyhalliMahadevaiah2023, author = {Kalishettyhalli Mahadevaiah, Mamathamba}, title = {Process development and electrical characterization of CMOS-integrated memristive devices for emerging non-volatile memory applications}, doi = {10.26127/BTUOpen-6557}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus4-65571}, school = {BTU Cottbus - Senftenberg}, year = {2023}, abstract = {Energy efficiency is vital for future low-power electronic applications. This ultra-low power consumption requirement enables the research beyond the conventional charge-based memories. Further, reliability, high scalability, fast switching, CMOS compatibility, high endurance, etc., are some of the characteristics envisaged by the new generation of emerging non-volatile memories (NVMs). A memristor or OxRAM is one among the many emerging NVMs, which can exhibit the aforementioned characteristics, and it has the potential to replace the power-hungry conventional NVMs. The memristive devices have the advantage of monolithic integration with the CMOS logic, which enables the widening of their application areas. Despite their various advantages, the reliability, forming voltages, and variability of the devices pose a hurdle to their wide commercial usage. Hence, it is crucial to identify these factors and mitigate them. This thesis addresses these issues through fabrication process improvements, electrical characterization techniques, and device-engineering methods. The improvements in the fabrication processes reduced the pristine state currents of the memristive devices. It impacted the reliability and resistive switching performance of the memristive devices directly. To further improve the performance, the memristive devices are integrated into the 130 nm BiCMOS baseline technology of IHP. Additionally, dedicated test structures are developed to monitor and control the fabrication process steps through in-line electrical characterization. Further, the forming current and voltage values, along with their dispersions in the 4 kbit memristive arrays, were reduced by utilizing the electrical characterization techniques. Accordingly, the forming operations were performed at high operating temperatures using incremental step pulse and verify algorithm (ISPVA). In contrast to the well-known method of increasing the current compliance (1R) or the gate voltage of the transistor (1T-1R) to increase the conduction filament size, a thin layer of Al2O3 is added. This device engineering technique reduced the variability in both LRS and HRS currents of the memristive devices. Additionally, the conduction filament properties in both states are modeled by using the quantum point contact (QPC) model. Finally, harnessing the intrinsic variability of the memristive devices for neuromorphic computing applications is demonstrated. The reliability of the devices is assessed through endurance and retention characteristics.}, subject = {Memristive devices; RRAM; ISPVA; Forming; Variability; Formierspannung; Variabilit{\"a}t; Dispersion; Leitungsdraht; Neuromorphe Anwendungen; CMOS; Nichtfl{\"u}chtiger Speicher; Memristor; Modellierung; Dispersion}, language = {en} }