@phdthesis{Zeidler2013, author = {Zeidler, Steffen}, title = {Enabling functional tests of asynchronous circuits using a test processor solution}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-29643}, school = {BTU Cottbus - Senftenberg}, year = {2013}, abstract = {During the last years, the asynchronous design style has been rediscovered as a potential solution to upcoming design issues in deep-submicron technologies. However, besides the lack of commercial tools supporting this design style, one major challenge is the test of asynchronous designs. Especially their event-driven behavior leads to problems during test. Basically, the timing of asynchronous circuits is determined by gate and wire delays that are sensitive to variations of environmental parameters (process, voltage and temperature). This leads to uncertainties in the timing of the responses. Consequently, standard commercial test systems cannot be used, because such systems read the responses at specific cycles and, therefore, could reject fault-free devices. Furthermore, available hardware testers are, in principle, not designed to react to signal events from the design-under-test as it is necessary to establish asynchronous communication via handshake signalling. As a result, even simple functional tests that only apply stimuli and read the responses of the design-under-test cannot be realized without preparatory measures. This work addresses these issues and proposes a concept to enable functional tests of asynchronous designs. The concept is based on a special test processor that provides generic interfaces used to establish asynchronous handshake communication with a device-under-test. By this, elastic functional tests can be realized that overcome the static timing of conventional tests and emulate the real operating environment of the design. Apart from the generic test processor architecture, an essential part of the concept deals with the establishment of the processor as a stand alone or embedded test equipment. A workflow is provided that describes how the device-under-test can be embedded into the test processor environment for performing the tests. Besides the interconnection between the asynchronous design and the test processor, this especially includes the generation of programs that realize the functional tests of the design. A methodology is introduced that generates the desired programs for the processor from a standard functional simulation of the design-under-test. Based on the generic concept, a framework including both a test processor implementation and the realization of the program generation is delivered. In order to evaluate the entire concept, this framework has been applied to functionally test an asynchronous arithmetic-logic-unit. In combination with additional experiments, conducted to determine the required resources, it has been shown that the introduced concept is a suitable approach to test asynchronous designs.}, subject = {Asynchrones Schaltwerk; Pr{\"u}ftechnik; Fehlererkennung; Asynchrone Schaltungen; Funktionaltest; Testprozessor; Transferprotokoll; Nichtdeterminismus; Asynchronous circuits; Functional test; Test processor; Transfer protocol; Nondeterminism}, language = {en} } @phdthesis{Petrovic2013, author = {Petrovic, Vladimir}, title = {Design methodology for highly reliable digital ASIC designs applied to network-centric system middleware switch processor}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:co1-opus-29620}, school = {BTU Cottbus - Senftenberg}, year = {2013}, abstract = {The sensitivity of application-specific integrated circuits (ASICs) to single event effects (SEE) can lead to failures of subsystems which are exposed to increased radiation levels in space and on the ground. The work described in this thesis presents a design methodology for a fully fault-tolerant ASIC that is immune to single event upset effects (SEU) in sequential logic, single event transient effects (SET) in combinatorial logic, and single event latchup effects (SEL). Redundant circuits combined with SEL power switches (SPS) are the basis for a design methodology which achieves this goal. Within the standard ASIC design flow enhancements were made in order to incorporate redundancy and SPS cells and, consequently, enable protection against SEU, SET, and SEL. In order to validate the resulting fault-tolerant circuits a fault-injection environment with carefully designed fault models was developed. The moments of fault occurrence and their durations are modeled according to the real effects in actual hardware. The proposed design methodology was applied to an innovative space craft area network (SCAN) central processor unit, known as middleware switch processor. The measurement results presented in this thesis prove the correct functionality of DMR and SPS circuits, as well as the high fault-tolerance of the implemented ASICs along with moderate overhead with respect to power consumption and occupied silicon area. Irradiation measurements demonstrated the correct design and successful implementation of the SPS cell.}, subject = {Kundenspezifische Schaltung; Schaltungsentwurf; Fehlertoleranz; Entwurfsmethodik; Single Event Effects; Latchup Schutz; ASIC Entwurf; Fault-tolerance; Design methodology; Single event effects; Latchup protection; ASIC design}, language = {en} }