FG Verteilte Systeme und Betriebssysteme
Refine
Document Type
Way of publication
- Open Access (2)
Language
- English (16)
Keywords
Institute
BTU
Assessing the Feasibility of Combined BLE and Wi-Fi Communication for High Data Sensing Applications
(2023)
Advanced sensors generate more data than can be transmitted using classic battery-powered wireless sensor networks. While using Wi-Fi would provide plenty of throughput, the receivers are energy hungry and, thus, the radio time needs to be reduced. Previous research suggests to combine Wi-Fi with low-power technologies such as BLE for an energy efficient coordination of the Wi-Fi radios. Existing approaches focus on individual point-to-point routes whereas certain applications require concurrent transmissions. We evaluated the combination of BLE and Wi-Fi on the ESP32-S3 multi-radio microcontroller through detailed energy and throughput measurements. The results show that established BLE connections allow to activateWi-Fi quickly on-demand; the energy efficiency of the data transmission is significantly improved over previous works but the BLE connection setup is prohibitively slow. While the combination of BLE and Wi-Fi provides high throughput with good energy efficiency, careful design of the BLE-based signalling protocol is necessary to also achieve low latency.
Unmanned Aerial Vehicles (UAVs) are evolving as adaptable platforms for a wide range of applications such as precise inspections, emergency response, and remote sensing.
Autonomous UAV swarms require efficient and stable communication during deployment for a successful mission execution. For instance, the periodic exchange of telemetry data between all swarm members provides the foundation for formation flight and collision avoidance. However, due to the mobility of the vehicles and instability of wireless transmissions, maintaining a secure and reliable all-to-all communication remains challenging.
This paper investigates encrypted and authenticated multi-hop broadcast communication based on the transmission of custom IEEE 802.11 Wi-Fi data frames.
Small Unmanned Aerial Vehicles (UAVs) have vast application potential from industrial logistics and disaster monitoring to smart farming, for example, to create maps with Normalized Difference Vegetation Index (NDVI) cameras and AI-based image classification or the precision spot application of fertilizers. Operating multiple UAVs in parallel, including those with different specializations, enables efficient coverage of large areas. While existing research focused mainly on predefined flight formations for swarms or autonomous missions for single UAVs, the focus of this work is on multiple UAVs with individually adaptable missions. We derive communication system requirements from swarm coordination algorithms and present a respective design. The resulting modular architecture enables future research on autonomous adaptive UAV swarms and their use as flying sensor platforms.
The tiny logic elements in modern integrated circuits increase the rate of transient failures significantly. Therefore, redundancy on various levels is necessary to retain reliability. However, for mixed-criticality scenarios, the typical processor designs offer either too little fault-tolerance or too much redundancy for one part of the applications. Amongst others, we specifically address redundant processor internal functional units (FU) to cope with transient errors and support wear leveling. A real-time operating system (RTOS) was extended to control our prototypical hardware platform and, since it can be configured deterministically within few clock cycles, we are able to reconfigure the FUs dynamically, at process switching time, according to the specified critically of the running processes. Our mechanisms were integrated into the Plasma processor and the Plasma-RTOS. With few changes to the original software code, it was, for example, possible to quickly change from fault-detecting to fault-correcting modes of the processor on demand.
Pseudo-Uniform Memory Architectures hide the memory's throughput bottlenecks and the network's latency differences in order to provide near-peak average throughput for computations on large datasets. This obviates the need for application-level partitioning and load balancing between NUMA domains but the performance of cross-core communication still depends on the actual placement of the involved variables and cores, which can result in significant variation within applications and between application runs.
This paper analyses the pseudo-uniform memory latency on the Intel Xeon Phi Knights Corner processor, derives strategies for the optimised placement of important variables, and discusses the role of localised coordination in pUMA systems. For example, a basic cache line ping-pong benchmark showed a 3x speedup between adjacent cores. Therefore, pUMA systems combined with support for controlled placement of small datasets are an interesting option when processor-wide load balancing is difficult while localised coordination is feasible.
Many-core architectures trade single-thread performance for a larger number of cores. Scalable throughput can be attained only by a high degree of parallelism, minimized synchronization. Whilst this is achievable for many applications, the operating system still introduces bottlenecks through non-local sharing, synchronization,, message passing. A particular challenge for highly dynamic applications, for example invasive HPC applications, elastic compute clouds, is the management of short-living application threads, processes. This paper discusses OS architecture choices based on microkernel, multikernel, distributed systems designs, our development experience in the context of the MyThOS project. Initial experiments show a much faster thread creation, activation compared to monolithic systems like Linux while providing a more flexible protection, threading model that is better suited for dynamic scenarios. However, despite significant progress in the overall domain of operating systems, the design space for scalable many-core operating systems is yet to be fully explored.
Hardware and software consistency protocols rely on global observability of consistency events. Acknowledged broadcast is an obvious choice to propagate these events. This paper presents a generalized ring topology for parallel event propagation with acknowledged delivery. Implementations for various many-core architectures show increased performance over conventional approaches. Therefore, diamond rings are a prime candidate for implementations of distributed memory models.
With the evolution toward fast networks of many-core processors, the design assumptions at the basis of software-level distributed shared memory (DSM) systems change considerably. But efficient DSMs are needed because they can significantly simplify the implementation of complex distributed algorithms. This paper discusses implications of the many-core evolution and derives a set of reusable elementary operations for future software DSMs. These elementary operations will help in exploring and evaluating new memory models and consistency protocols.
On many-core processors, both operating system kernels and bare metal applications need efficient cross-core coordination and communication. Although explicit shared- memory programming and message passing might provide the best performance, they also limit the system’s control over scheduling. In contrast, interrupt-driven cross-core invocations provide universal coordination mechanisms that also enable preemptive operations across cores. This paper surveys cross- core invocation mechanisms and their usability with respect to prevalent coordination scenarios. We integrated some of these mechanisms into a bare-metal environment for the Intel SCC pro- cessor and will discuss implementation aspects of the interrupt- driven invocations. In conclusion, such invocation mechanisms provide an expressive platform for future operating systems kernels and bare-metal applications.