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Institute
- FG Mikroelektronik (80)
This paper presents an 8-bit current steering DAC that uses unary current sources and a thermometer coded register. The thermometer coded register is controlled by sequentially stepping one or two steps up or down dependent on the control input. The enhanced step size mitigates the slew-rate limitation if the DAC is used in a delta-encoded tracking ADC. The sequential switching of thermometer coded DAC register does not require a binary to thermometer decoder and reduces complexity of error compensation.
This paper presents a modified interpolation algo-
rithm for signals with variable data rate from asynchronous
ADCs. The Adaptive weights Conjugate gradient Toeplitz
matrix (ACT) algorithm is extended to operate with a contin-
uous data stream. An additional preprocessing of data with
constant and linear sections and a weighted overlap of step-
by-step into spectral domain transformed signals improve the
reconstruction of the asycnhronous ADC signal. The interpo-
lation method can be used if asynchronous ADC data is fed
into synchronous digital signal processing.
This paper presents the design of a high-voltage (HV) rail-to-rail error amplifier. This circuit controls the output signal of a low drop-out voltage regulator (LDO) according to the reference voltages and based on stacked standard transistors. The circuit is designed using 65 nm CMOS process technology with a nominal voltage of 2.5 V and is optimized for arbitrary values of supply voltage up to 5.0 V. The error amplifier consists of 3 stages and 2 feedback loops. The stages are internally connected rail-to-rail to achieve high GBW and DC accuracy. The simulation and measurement results for the designed HV-error amplifier show that the output signal of the LDO tracks the reference voltages. The circuit design is technology-independent and compatible with scaled CMOS.
This paper presents a high-voltage (HV) driver for switching a buck converter. The circuit is based on 3-stacked CMOS using gate control circuits to drive maximum current which indicates minimized on-resistance of the HV-driver thus achieving faster switching. The circuit is designed and fabricated using 65 nm CMOS TSMC process technology with a nominal voltage of 2.5 V and with a supply voltage of 5.5 V. Since the design is based on stacked CMOS transistors, the circuit is technology-independent. The initial on-resistances of the driver pull-up and the pull-down paths have an improvement of 75% and 36% respectively. Due to a buck converter switched by the designed HV-driver, output voltages in the range of 0.45 V to 2.45 V can be achieved from different high supply voltages in the range of 3.5 V to 5.5 V. The circuit occupies an area of 0.187 mm2.
The design of an integrated receiver for reflected light using correlated double sampling (CDS) is presented. CDS has the disadvantage that input signals of high frequencies are folded back to the base band caused by sampling the continuous input signal. However, the circuit presented here uses a new method to limit the bandwidth of the CDS input signal. Two filter-capacitors, one for each clock phase, are periodically connected to the input of the CDS circuit. As the input signal is low-pass filtered by the ohmic output resistance of the optical sensor in conjuction with the filter-capacitors, aliasing can be avoided. Measurements of a test circuit demonstrate the effectiveness of this principle.
A novel type of signal processing for a magnetic micro torque sensor is described and simulated. The sensor principles are based on a soft magnetic core shaped as a yoke, two current-carrying coils, a soft magnetic amorphous ribbon with strong magnetostrictive properties that is fixed on a shaft, and at least two magnetic flux-density sensors. The sensor determines directly the change of permeability of the amorphous ribbon on the shaft. Nevertheless, the variation of the air gap between the sensor and the rotating shaft affects the measurement principle. Therefore, the magnetic flux density is measured at two positions, one at the face of the soft magnetic core and the other beside the face of the core in the area of the stray flux. The evaluation of these two flux densities yields the distance between the sensor and the shaft as well as the permeability of the amorphous ribbon. The problem arising with this practice is the determination of the sensitivity of the flux-density sensors. As the current-carrying coils are alternately operated in a common and a push-pull mode, the unknown sensitivities of the flux-density sensors do not affect the evaluation of the permeability of the amorphous ribbon on the shaft.
The characteristics of magnetic field-sensitive split-drain MOSFETs (MAGFETs) have been experimentally measured. The sensitivity depends on the geometry and the operating point of the MAGFET. Particular attention is paid to the lateral parasitic conductance between the split drains. The equivalent spectral noise density of the magnetic flux density is measured. Additionally, a macro-model of the MAGFET has been developed for SPICE.
This paper presents the design of a high-voltage driver with an adapted level shifter for switching converters. The proposed HV-driver and level shifter are based on stacked standard CMOS, therefore the design is technology independent. The circuit is designed in 65-nm TSMC technology with a nominal voltage of 2.5 V and optimized for arbitrary supply voltages from 2.6 V to 6.0 V. This range is extended by 41.7% when compared against common drivers and level shifters with the circuit being suitable for a supply voltage range of 2.4 V between 2.6 V and 5.0 V. The total area of the designed level shifter is about 3.8% of that required for similar circuit in previous work.
This paper presents two high-voltage circuits used in power management, a switching driver for buck converter with optimized on-resistance and a low dropout (LDO) voltage regulator with 2-stacked pMOS pass devices. The circuit design is based on stacked MOSFETs, thus the circuits are technology independent.
This paper presents the design of a high-voltage differential amplifier using six different pre-input stage circuits to reduce high-voltage input levels to low-voltage signals. The proposed circuits are designed using 65 nm CMOS process technology with a nominal voltage of 2.5 V and a supply voltage of 5 V. The designs are based on stacked low-voltage standard CMOS transistors. The different pre-input stage circuits are compared to each other in terms of their circuit description, drawbacks, advantages and simulation results. The principle of the five designed pre-input stage circuits can be applied to higher voltage range input signals as well.