This paper presents a modified interpolation algo-
rithm for signals with variable data rate from asynchronous
ADCs. The Adaptive weights Conjugate gradient Toeplitz
matrix (ACT) algorithm is extended to operate with a contin-
uous data stream. An additional preprocessing of data with
constant and linear sections and a weighted overlap of step-
by-step into spectral domain transformed signals improve the
reconstruction of the asycnhronous ADC signal. The interpo-
lation method can be used if asynchronous ADC data is fed
into synchronous digital signal processing.
This paper presents a 10-bit tracking ADC using a multi-bit quantiser and a segmented current-steering DAC. The quantiser allows a dynamical adjustment of the step size dependent on the input signal waveform. This mitigates the limited slew rate of delta encoded ADCs. Energy consumption induced by 1 LSB ripple is removed by the quantiser. The segmented current-steering DAC allows simple control, good monotonicity and improved transient response when compared to previous design as well as potential power reduction.
This paper presents the design of a high-voltage (HV) rail-to-rail error amplifier. This circuit controls the output signal of a low drop-out voltage regulator (LDO) according to the reference voltages and based on stacked standard transistors. The circuit is designed using 65 nm CMOS process technology with a nominal voltage of 2.5 V and is optimized for arbitrary values of supply voltage up to 5.0 V. The error amplifier consists of 3 stages and 2 feedback loops. The stages are internally connected rail-to-rail to achieve high GBW and DC accuracy. The simulation and measurement results for the designed HV-error amplifier show that the output signal of the LDO tracks the reference voltages. The circuit design is technology-independent and compatible with scaled CMOS.
This paper presents an 8-bit current steering DAC that uses unary current sources and a thermometer coded register. The thermometer coded register is controlled by sequentially stepping one or two steps up or down dependent on the control input. The enhanced step size mitigates the slew-rate limitation if the DAC is used in a delta-encoded tracking ADC. The sequential switching of thermometer coded DAC register does not require a binary to thermometer decoder and reduces complexity of error compensation.