We report on the structural and electrical properties of Pr-based high-k dielectric films fabricated by solid-state reaction between metallic Pr and SiO2 underlayers. A non-destructive depth profiling using synchrotron radiation excited photoelectron spectroscopy (SR-PES), X-ray photoelectron spectroscopy (XPS) and transmission electron microscopy (TEM) were employed to examine the chemical composition and microstructure. Ab initio calculations were done to gain insight into the physical processes involved. SR-PES results indicate that Pr deposition at room temperature (RT) leads to the formation of a Pr silicide and a Pr oxide, what is in good agreement with the scenario expected from ab initio calculations. As revealed by TEM and electrical measurements, oxidation of the reacted structures, followed by annealing, results in a stacked dielectric composed of a SiO2-based buffer with an enhanced permittivity and a Pr silicate film with a high dielectric constant. The leakage current density of 10-4 A/cm2 was measured for stacks with capacitance equivalent thickness (CET) of 1.5 nm prepared by evaporation of the Pr layer on a 1.8 nm SiO2 film, followed by oxidation in air ambient and annealing in N2 atmosphere. The capacitance-voltage (C-V) curves exhibit a large flatband voltage (VFB) shift indicating the presence of a positive charge in the stack. Switching away from the Al contacts to Au gate electrodes introduces a significant reduction of the VFB by 1.3 eV, what is much more than the change expected from the work function difference between Al and Au (not, vert, similar0.9 eV). This in turn implies that VFB is strongly affected by the gate interface electrode.
A cascode amplifier stage with an isolated NLDMOS and SiGe:C HBT was demonstrated. The main advantages of that circuitry concept are a reduced capacitive portion of the input impedance and a significantly increased power gain in comparison to a single NLDMOS amplifier stage. Additionally a more stable input impedance for different RF input power levels can be obtained. The stable and less capacitive input impedance simplifies the design of integrated impedance matching networks. In a first feasibility study a circuit with a NLDMOS gate width of 90 μm showed a maximum gain of 18 dB and a maximum output power of 10 dBm at 11 GHz. To the authors knowledge the circuit concept of a cascode amplifier containing a HBT and an isolated NLDMOS is presented for the first time.