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Many-core architectures trade single-thread performance for a larger number of cores. Scalable throughput can be attained only by a high degree of parallelism, minimized synchronization. Whilst this is achievable for many applications, the operating system still introduces bottlenecks through non-local sharing, synchronization,, message passing. A particular challenge for highly dynamic applications, for example invasive HPC applications, elastic compute clouds, is the management of short-living application threads, processes. This paper discusses OS architecture choices based on microkernel, multikernel, distributed systems designs, our development experience in the context of the MyThOS project. Initial experiments show a much faster thread creation, activation compared to monolithic systems like Linux while providing a more flexible protection, threading model that is better suited for dynamic scenarios. However, despite significant progress in the overall domain of operating systems, the design space for scalable many-core operating systems is yet to be fully explored.
The electronic structure of the CdS/Cu2ZnSnS4 (CZTS) heterojunction was investigated by direct and inverse photoemission. The effects of a KCN etch of the CZTS absorber prior to CdS deposition on the band alignment at the respective interface were studied. We find a “cliff”-like conduction band offset at the CdS/CZTS interface independent of absorber pretreatment and a significant etch-induced enhancement of the energetic barrier for charge carrier recombination across the CdS/CZTS interface.
The chemical and electronic surface structure of Cu2ZnSnS4 thin-film solar cell absorbers has been investigated by direct and inverse photoemission. Particular emphasis was placed on the impact of KCN etching, which significantly alters the surface composition and is best explained by a preferred etching of Cu and, to a lesser degree, Sn. As a consequence the surface band gap increased from (1.53 +/- 0.15) eV, which agrees with optically derived bulk band gap values, to (1.91 +/- 0.15) ev.
This work presents a quasi-static electrical characterization of 1-transistor-1-resistor memristive structures designed following hardness-by-design techniques integrated in the CMOS fabrication process to assure multi-level capabilities in harsh radiation environments. Modulating the gate voltage of the enclosed layout transistor connected in series with the memristive device, it was possible to achieve excellent switching capabilities from a single high resistance state to a total of eight different low resistance states (more than 3 bits). Thus, the fabricated devices are suitable for their integration in larger in-memory computing systems and in multi-level memory applications.
Index Terms—radiation-hard, hardness-by-design, memristive
devices, Enclosed Layout Transistor, in-memory computing