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For the fabrication of modern graphene devices, uniform growth of high-quality monolayer graphene on wafer scale is important. This work reports on the growth of large-scale graphene on semiconducting 8 inch Ge(110)/Si wafers by chemical vapor deposition and a DFT analysis of the growth process. Good graphene quality is indicated by the small FWHM (32 cm–1) of the Raman 2D band, low intensity ratio of the Raman D and G bands (0.06), and homogeneous SEM images and is confirmed by Hall measurements: high mobility (2700 cm2/Vs) and low sheet resistance (800 Ω/sq). In contrast to Ge(001), Ge(110) does not undergo faceting during the growth. We argue that Ge(001) roughens as a result of vacancy accumulation at pinned steps, easy motion of bonded graphene edges across (107) facets, and low energy cost to expand Ge area by surface vicinals, but on Ge(110), these mechanisms do not work due to different surface geometries and complex reconstruction.
Study on the metal -graphene contact resistance achieved with one -dimensional contact architecture
(2023)
Graphene has always been considered as one of the materials with the greatest potential for the realization of improved microelectronic and photonic devices. But to actually reach its full potential in Si CMOS technology, graphene
-based devices need to overcome different challenges. They do not only
need to have better performances than standard devices, but they also need to be compatible with the production of standard Si based devices. To address the first challenge the main route requires the optimization of the contact resistance, that highly reduces the devices performance, while the second challenges requires the integration of graphene inside the standard production lines used for microelectronic. In this work we used an 8” wafer pilot -line to realize our devices and we studied the behavior of the contact resistance between metal and graphene obtained by one -dimensional contact architecture between the two materials. The contact resistance has been measured by means of Transmission Line Method (TLM) with several contact patterning.
Due to the unique electronic band structure, graphene has opened great potential to extend the functionality of a large variety of devices. Despite the significant progress in the fabrication of various graphene based microelectronic devices, the integration of graphene devices still lack the stability and compatibility with Si-technology processes. Therefore, the investigation and preparation of graphene devices in conditions resembling as close as possible the Si technology environment is of highest importance. This study aims to explore various aspects of graphene research on a 200mm pilot line, with a focus on simulations and fabrication of graphene modulator. To be more precise, it includes design and fabrication of the layouts, necessary mask sets, creation of the flows, fabrication, and measurements of the Gr modulators on 200 mm wafers.
Due to the unique electronic structures, graphene and other 2D Materials are considered as materials which can enable and extend the functionalities and performance in a large variety of applications, among them in microelectronics. At this point, the investigation and preparation of graphene devices in conditions resembling as close as possible the Si technology environment is of highest importance.Towards these goals, this paper focuses on the full spectra of graphene research aspects in 200mm pilot line. We investigated different process module developments such as CMOS compatible growth of high quality graphene on germanium and its growth mechanisms, transfer related challenges on target substrates, patterning, passivation and various concepts of contacting of graphene on a full 200 mm wafers. Finally, we fabricated proof-of-concept test structures e.g. TLM, Hall bars and capacitor structures to prove the feasibility of graphene processing in the pilot line of IHP.