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For the integration of 100 % Ge onto the Si platform, a buffer oxide approach has been developed recently, using rare earth oxides to tune the lattice constant between the Si and the Ge. Among these buffer oxides, PrO2 is a prospective candidate with high quality crystalline growth on Si, moderated by an interfacial Pr-silicate between. In order to specify electronic properties of thin PrO2 and its interface on Si(111), especially the width of the band gap, we performed synchrotron radiation based XPS, UPS and XAS measurements at the U49/2 PGM 2 beamline at BESSY II and correlate the results with our structural characterisation performed by TEM and XRD. In order to evaluate the dielectric properties of thin PrO2 layers on Si(111), we performed temperature-, time-, voltage-, and layer thickness-dependent leakage current measurements (J-V). Here, we identified relaxation behaviour in the leakage current, successfully addressed to defect like states inside the Pr-silicate interface layer, corroborated by frequency dependent capacitance versus voltage (C-V) measurements.
We report on the structural and electrical properties of Pr-based high-k dielectric films fabricated by solid-state reaction between metallic Pr and SiO2 underlayers. A non-destructive depth profiling using synchrotron radiation excited photoelectron spectroscopy (SR-PES), X-ray photoelectron spectroscopy (XPS) and transmission electron microscopy (TEM) were employed to examine the chemical composition and microstructure. Ab initio calculations were done to gain insight into the physical processes involved. SR-PES results indicate that Pr deposition at room temperature (RT) leads to the formation of a Pr silicide and a Pr oxide, what is in good agreement with the scenario expected from ab initio calculations. As revealed by TEM and electrical measurements, oxidation of the reacted structures, followed by annealing, results in a stacked dielectric composed of a SiO2-based buffer with an enhanced permittivity and a Pr silicate film with a high dielectric constant. The leakage current density of 10-4 A/cm2 was measured for stacks with capacitance equivalent thickness (CET) of 1.5 nm prepared by evaporation of the Pr layer on a 1.8 nm SiO2 film, followed by oxidation in air ambient and annealing in N2 atmosphere. The capacitance-voltage (C-V) curves exhibit a large flatband voltage (VFB) shift indicating the presence of a positive charge in the stack. Switching away from the Al contacts to Au gate electrodes introduces a significant reduction of the VFB by 1.3 eV, what is much more than the change expected from the work function difference between Al and Au (not, vert, similar0.9 eV). This in turn implies that VFB is strongly affected by the gate interface electrode.