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Aussetzbarer Taktgenerator
(2008)
GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated Circuits
(2016)
Frequency-Domain Modeling of Ground Bounce and Substrate Noise for Synchronous and GALS Systems
(2015)
Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on- line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system.
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems
(2019)
The Effects of Voltage Scaling on Reliability and Power Consumption in Multiprocessor Systems
(2018)
RRAM technology is a promising candidate for implementing efficient AI accelerators with extensive multiply-accumulate operations. By scaling RRAM devices to the synaptic crossbar array, the computations can be realized in situ, avoiding frequent weights transfer between the processing units and memory. Besides, as the computations are conducted in the analog domain with high flexibility, applying multilevel input voltages to the RRAM devices with multilevel conductance states enhances the computational efficiency further. However, several non-idealities existing in emerging RRAM technology may degrade the reliability of the system. In this paper, we measured and investigated the impact of read disturb on RRAM devices with different input voltages, which incurs conductance drifts and introduces errors. The measured data are deployed to simulate the RRAM based AI inference engines with multilevel states.
A Substrate Noise Reduction Methodology Based on Power Domain Separation of GALS Subcomponents
(2017)
Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of 8x8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices’ nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems.
A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study
(2017)
A Mid Value-Select Voter
(2005)
Aussetzbarer Taktgenerator
(2009)
An Overview of the Modeling and Simulation of the Single Event Transients at the Circuit Level
(2017)
An Overview of the Current Models for the Circuit-level Simulations of Single Event Transients
(2017)