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In this work we present the progress in regard to the integration of a surface plasmon resonance refractive index sensor into a CMOS compatible 200 mm wafer silicon-based technology. Our approach pursues the combination of germanium photodetectors with metallic nanohole arrays. The paper is focused on the technology development to fabricate large area photodetectors based on a modern design concept. In a first iteration we achieved a leakage current density of 82 mA/cm2 at reverse bias of 0.5 V and a maximum optical responsivity of 0.103 A/W measured with TE polarized light at λ = 1310 nm and a reversed bias of 1 V. For the realization of nanohole arrays we used thin Titanium nitride (TiN) layers deposited by a sputtering process. We were able to produce very homogenous TiN layers with a thickness deviation of around 10 % and RMS of 1.413 nm for 150 nm thick TiN layers.
The resistive switching properties of HfO2 based 1T-1R memristive devices are electrically modified by adding ultra-thin layers of Al2O3
into the memristive device. Three different types of memristive stacks are fabricated in the 130 nm CMOS technology of IHP. The switching properties of the memristive devices are discussed with respect to forming voltages, low resistance state and high resistance state characteristics and their variabilities. The experimental I–V characteristics of set and reset operations are evaluated by using the quantum point contact model. The properties of the conduction filament in the on and off states of the memristive devices are discussed with respect to the model parameters obtained from the QPC fit.
The Fraunhofer Institute for Photonic Microsystems (Fraunhofer IPMS) develops spatial light modulators (SLMs) based on arrays of tiltable micro mirrors on a semiconductor chip. Typical applications are pattern generation for deepUV-laser mask writing or structured illumination in microscopy. Development and optimization of such SLMs requires detailed knowledge of the device behaviour under operating conditions. Here, the flatness of each single mirror effects the image resolution and contrast of the generated pattern and is amongst others a characteristic property of SLMs. In this context a surface topography measurement under laser exposure (in situ) was designed. The interferometric setup uses the phase-shift principle and allows a resolution in z-direction in the single-digit nanometer range. During irradiation with UV-laser light at 248 nm (KrF) and energy densities of up to 20 mJ/cm2 the change in single micro-mirrors topography was detected in situ. Measurementswith varying pulse energies
were carried out to identify an impacton the device
performance. In general, the setup is neither limited to a
specific illumination wavelength nor to micro-mirrors as structures under test.
Due to the unique electronic structures, graphene and other 2D Materials are considered as materials which can enable and extend the functionalities and performance in a large variety of applications, among them in microelectronics. At this point, the investigation and preparation of graphene devices in conditions resembling as close as possible the Si technology environment is of highest importance.Towards these goals, this paper focuses on the full spectra of graphene research aspects in 200mm pilot line. We investigated different process module developments such as CMOS compatible growth of high quality graphene on germanium and its growth mechanisms, transfer related challenges on target substrates, patterning, passivation and various concepts of contacting of graphene on a full 200 mm wafers. Finally, we fabricated proof-of-concept test structures e.g. TLM, Hall bars and capacitor structures to prove the feasibility of graphene processing in the pilot line of IHP.
Integrated optical interconnections in silicon chips have the potential to replace electrical interconnects between integrated circuits thanks to their high bandwidth and low energy communication promises. A silicon dielectric waveguide can be etched through the full thickness of a silicon substrate providing a monolithically integrated solution for 2.5D and 3D photonic architectures. The optical through-silicon waveguide design presented here is based on Finite Difference Time Domain simulations, while the fabrication takes advantage of the innovative plasma cryo-etching process that provides smooth sidewalls and tapering angle tunability. Such structures can provide effective mode size conversion, therefore favoring the coupling of external light sources to photonic integrated circuits and the stacking of multiple optically interconnected dies.
Optical interconnections are a promising step for-ward to overcome the intrinsic limitations of electrical inter-connections in integrated circuits. In this work, we present a finite element method (FEM) simulation study of a dielectric waveguide etched through the full thickness of a silicon substrate. In particular, it is investigated the effect of the bridge-to-core size ratio on the first two supported modes. Then, the influence of the waveguide sidewalls tapering angle on the three-dimensional beam propagation is studied. Such optical through-silicon waveguide (OTSW), if nonadiabatically tapered can provide effective mode size conversion and favour the coupling of external light sources to photonic integrated circuits.