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In-Memory Communication Mechanisms for Many-Cores – Experiences with the Intel SCC

  • Many-core processors combine fast on-chip communication with access to large amounts of shared memory. This makes it possible to exploit the benefits of distributed as well as shared memory programming models within single parallel algorithms. While large amounts of data can be shared in the memory and caches, coordinating the activities of hundreds of cores relies on cross core communication mechanisms with ultra low latency for very small messages. In this paper we discuss two communication protocols for the Intel SCC and compare them to the MPI implementation of the SCC. Our micro-benchmark results underline that special purpose protocols for small messages make much finer levels of parallelism possible than general purpose message passing systems. Index Terms—many-core, message passing, shared memory

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Author: Randolf Rotta, Thomas Prescher, Jana Traue, Jörg Nolte
URL:http://www.tacc.utexas.edu/documents/13601/4234acca-2171-4465-aa48-7592d5e577f9
URL:http://www.tacc.utexas.edu/documents/13601/06d702ab-3f48-4942-9b07-2fbd880d4310
URL:http://www.tacc.utexas.edu/ti-hpcs12
Title of the source (English):TACC-Intel Highly Parallel Computing Symposium (TIHPCS), Austin/Texas, 2012
Document Type:Conference publication peer-reviewed
Language:English
Year of publication:2012
Faculty/Chair:Fakultät 1 MINT - Mathematik, Informatik, Physik, Elektro- und Informationstechnik / FG Theoretische Informatik
Fakultät 1 MINT - Mathematik, Informatik, Physik, Elektro- und Informationstechnik / FG Verteilte Systeme und Betriebssysteme
Institution name at the time of publication:Fakultät für Mathematik, Naturwissenschaften und Informatik (eBTU) / LS Theoretische Informatik
Fakultät für Mathematik, Naturwissenschaften und Informatik (eBTU) / LS Verteilte Systeme / Betriebssysteme
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