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Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages

  • RRAM technology is a promising candidate for implementing efficient AI accelerators with extensive multiply-accumulate operations. By scaling RRAM devices to the synaptic crossbar array, the computations can be realized in situ, avoiding frequent weights transfer between the processing units and memory. Besides, as the computations are conducted in the analog domain with high flexibility, applying multilevel input voltages to the RRAM devices with multilevel conductance states enhances the computational efficiency further. However, several non-idealities existing in emerging RRAM technology may degrade the reliability of the system. In this paper, we measured and investigated the impact of read disturb on RRAM devices with different input voltages, which incurs conductance drifts and introduces errors. The measured data are deployed to simulate the RRAM based AI inference engines with multilevel states.

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Metadaten
Author: Jianan Wen, Andrea Baroni, Eduardo Perez, Markus Ulbricht, Christian WengerORCiD, Milos Krstic
DOI:https://doi.org/10.1109/DFT56152.2022.9962345
ISBN:978-1-6654-5938-9
ISBN:978-1-6654-5937-2
ISSN:2765-933X
Title of the source (English):2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Document Type:Conference publication peer-reviewed
Language:English
Year of publication:2022
Tag:AI accelarator; Multilevel switching; RRAM
First Page:1
Last Page:6
Faculty/Chair:Fakultät 1 MINT - Mathematik, Informatik, Physik, Elektro- und Informationstechnik / FG Halbleitermaterialien
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