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Optimized programming algorithms for multilevel RRAM in hardware neural networks

  • A key requirement for RRAM in neural network accelerators with a large number of synaptic parameters is the multilevel programming. This is hindered by resistance imprecision due to cycle-to-cycle and device-to-device variations. Here, we compare two multilevel programming algorithms to minimize resistance variations in a 4-kbit array of HfO 2 RRAM. We show that gate-based algorithms have the highest reliability. The optimized scheme is used to implement a neural network with 9-level weights, achieving 91.5% (vs. software 93.27%) in MNIST recognition.

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Author: Valerio Milo, Francesco Anzalone, Cristian Zambelli, Eduardo Perez, Mamathamba Kalishettyhalli Mahadevaiah, Óscar G. Ossorio, Piero Olivo, Christian WengerORCiD, Daniele Ielmini
DOI:https://doi.org/10.1109/IRPS46558.2021.9405119
ISBN:978-1-7281-6894-4
ISSN:1938-1891
Title of the source (English):IEEE International Reliability Physics Symposium (IRPS), 2021
Document Type:Conference publication peer-reviewed
Language:English
Year of publication:2021
Tag:Multilevel switching; RRAM; memristive switching; neural network
Faculty/Chair:Fakultät 1 MINT - Mathematik, Informatik, Physik, Elektro- und Informationstechnik / FG Halbleitermaterialien
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