• search hit 37 of 37
Back to Result List

One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing

  • The use of resistive random-access memory (RRAM) for in-memory computing (IMC) architectures has significantly improved the energy-efficiency of artificial neural networks (ANN) over the past years. Current RRAM-technologies are physically limited to a defined unambiguously distinguishable number of stable states and a maximum resistive value and are compatible with present complementary metal-oxide semiconductor (CMOS)-technologies. In this work, we improved the accuracy of current ANN models by using increased weight resolutions of memristive devices, combining two or more in-series RRAM cells, integrated in the back end of line (BEOL) of the CMOS process. Based on system level simulations, 1T2R devices were fabricated in IHP's 130nm SiGe:BiCMOS technology node, demonstrating an increased number of states. We achieved an increase in weight resolution from 3 bit in ITIR cells to 6.5 bit in our 1T2R cell. The experimental data of 1T2R devices gives indications for the performance and energy-efficiency improvement in ITNR arrays forThe use of resistive random-access memory (RRAM) for in-memory computing (IMC) architectures has significantly improved the energy-efficiency of artificial neural networks (ANN) over the past years. Current RRAM-technologies are physically limited to a defined unambiguously distinguishable number of stable states and a maximum resistive value and are compatible with present complementary metal-oxide semiconductor (CMOS)-technologies. In this work, we improved the accuracy of current ANN models by using increased weight resolutions of memristive devices, combining two or more in-series RRAM cells, integrated in the back end of line (BEOL) of the CMOS process. Based on system level simulations, 1T2R devices were fabricated in IHP's 130nm SiGe:BiCMOS technology node, demonstrating an increased number of states. We achieved an increase in weight resolution from 3 bit in ITIR cells to 6.5 bit in our 1T2R cell. The experimental data of 1T2R devices gives indications for the performance and energy-efficiency improvement in ITNR arrays for ANN applications.show moreshow less

Export metadata

Additional Services

Search Google Scholar
Metadaten
Author: Max Uhlmann, Emilio Pérez-Bosch Quesada, Markus Fritscher, Eduardo Pérez, Markus Andreas Schubert, Marc ReichenbachORCiD, Philip Ostrovskyy, Christian WengerORCiD, Gerhard Kahmen
DOI:https://doi.org/10.1109/NEWCAS57931.2023.10198073
ISBN:979-8-3503-0024-6
ISBN:979-8-3503-0025-3
ISSN:2474-9672
ISSN:2472-467X
Title of the source (English):21st IEEE Interregional NEWCAS Conference (NEWCAS)
Publisher:Institute of Electrical and Electronics Engineers (IEEE)
Document Type:Conference publication peer-reviewed
Language:English
Year of publication:2023
Tag:In-Memory Computing; RRAM
Number of pages:5
Article number:23547179
Faculty/Chair:Fakultät 1 MINT - Mathematik, Informatik, Physik, Elektro- und Informationstechnik / FG Halbleitermaterialien
Einverstanden ✔
Diese Webseite verwendet technisch erforderliche Session-Cookies. Durch die weitere Nutzung der Webseite stimmen Sie diesem zu. Unsere Datenschutzerklärung finden Sie hier.