TY - CHAP A1 - Schrape, Oliver A1 - Grass, Eckhard A1 - Petri, Markus A1 - Zeidler, Steffen A1 - Jagdhold, Ulrich A1 - Winkler, Frank T1 - An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis Y1 - 2010 ER - TY - CHAP A1 - Zeidler, Steffen A1 - Bystrov, Alexander A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - On-line Testing of Bundled-Data Asynchronous Handshake Protocols Y1 - 2010 ER - TY - CHAP A1 - Zeidler, Steffen A1 - Ehrig, Marcus A1 - Krstic, Milos A1 - Augustin, Michael A1 - Wolf, Christoph A1 - Kraemer, Rolf T1 - Ultra Low Cost Asynchronous Handshake Checker Y1 - 2009 ER - TY - CHAP A1 - Wolf, Christoph A1 - Zeidler, Steffen A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Overview on ATE Test and Debugging Methods for Asynchronous Circuits Y1 - 2011 ER - TY - CHAP A1 - Babic, Milan A1 - Zeidler, Steffen A1 - Krstic, Milos T1 - GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated Circuits T2 - 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2016), 8-11 May, Porto Alegre, Brazil, 2016 Y1 - 2016 SN - 978-1-4673-9007-1 SP - 67 EP - 74 PB - IEEE CY - Piscataway, NJ ER - TY - PAT A1 - Zeidler, Steffen T1 - Prüfschaltung zur Prüfung einer Durchführung eines Handshake-Protokolls und Verfahren zur Prüfung einer Durchführung eines Handshake-Protokolls Y1 - 2010 ER -