TY - GEN A1 - Mannocci, Piergiulio A1 - Baroni, Andrea A1 - Melacarne, Enrico A1 - Zambelli, Cristian A1 - Olivo, Piero A1 - Perez, Eduardo A1 - Wenger, Christian A1 - Ielmini, Daniele T1 - In-Memory Principal Component Analysis by Crosspoint Array of Rresistive Switching Memory T2 - IEEE Nanotechnology Magazine N2 - In Memory Computing (IMC) is one of the most promising candidates for data-intensive computing accelerators of machine learning (ML). A key ML algorithm for dimensionality reduction and classification is principal component analysis (PCA), which heavily relies on matrixvector multiplications (MVM) for which classic von Neumann architectures are not optimized. Here, we provide the experimental demonstration of a new IMCbased PCA algorithm based on power iteration and deflation executed in a 4-kbit array of resistive switching random-access memory (RRAM). The classification accuracy of the Wisconsin Breast Cancer data set reaches 95.43%, close to floatingpoint implementation. Our simulations indicate a 250× improvement in energy efficiency compared to commercial GPUs, thus supporting IMC for energy-efficient ML in modern data-intensive computing. KW - RRAM KW - Multilevel switching KW - neural network Y1 - 2022 U6 - https://doi.org/10.1109/MNANO.2022.3141515 SN - 1932-4510 VL - 16 IS - 2 SP - 4 EP - 13 ER - TY - GEN A1 - Rizzi, Tommaso A1 - Baroni, Andrea A1 - Glukhov, Artem A1 - Bertozzi, Davide A1 - Wenger, Christian A1 - Ielmini, Daniele A1 - Zambelli, Cristian T1 - Process-Voltage-Temperature Variations Assessment in Energy-Aware Resistive RAM-Based FPGAs T2 - IEEE Transactions on Device and Materials Reliability N2 - Resistive Random Access Memory (RRAM) technology holds promises to improve the Field Programmable Gate Array (FPGA) performance, reduce the area footprint, and dramatically lower run-time energy requirements compared to the state-of-the-art CMOS-based products. However, the integration of RRAM in FPGAs is hindered by the high programming power consumption and by non-ideal behaviors of the device due to its stochastic nature that may overshadow the benefits in normal operation mode. To cope with these challenges, optimized programming strategies have to be investigated. In this work, we explore the impact that different procedures to set the device have on the run-time performance. Process, voltage, and temperature (PVT) variations as well as time-dependent drift effect of the RRAM device are considered in the assessment of 4T1R MUX designs characteristics. The comparison with tradition CMOS implementations reveals how the choice of the target resistive state and the programming algorithm are key design aspects to reduce the run-time delay and energy metrics, while at the same time improving the robustness against the different sources of variations. KW - RRAM KW - FPGA Y1 - 2023 U6 - https://doi.org/10.1109/TDMR.2023.3259015 SN - 1530-4388 VL - 23 IS - 3 SP - 328 EP - 336 ER - TY - GEN A1 - Baroni, Andrea A1 - Glukhov, Artem A1 - Perez, Eduardo A1 - Wenger, Christian A1 - Calore, Enrico A1 - Schifano, Sebastiano Fabio A1 - Olivo, Piero A1 - Ielmini, Daniele A1 - Zambelli, Cristian T1 - An energy-efficient in-memory computing architecture for survival data analysis based on resistive switching memories T2 - Frontiers in Neuroscience N2 - One of the objectives fostered in medical science is the so-called precision medicine, which requires the analysis of a large amount of survival data from patients to deeply understand treatment options. Tools like Machine Learning and Deep Neural Networks are becoming a de-facto standard. Nowadays, computing facilities based on the Von Neumann architecture are devoted to these tasks, yet rapidly hitting a bottleneck in performance and energy efficiency. The In-Memory Computing (IMC) architecture emerged as a revolutionary approach to overcome that issue. In this work, we propose an IMC architecture based on Resistive switching memory (RRAM) crossbar arrays to provide a convenient primitive for matrix–vector multiplication in a single computational step. This opens massive performance improvement in the acceleration of a neural network that is frequently used in survival analysis of biomedical records, namely the DeepSurv. We explored how the synaptic weights mapping strategy and the programming algorithms developed to counter RRAM non-idealities expose a performance/energy trade-off. Finally, we assessed the benefits of the proposed architectures with respect to a GPU-based realization of the same task, evidencing a tenfold improvement in terms of performance and three orders of magnitude with respect to energy efficiency. KW - RRAM KW - In-Memory Computing KW - Multilevel switching Y1 - 2022 U6 - https://doi.org/10.3389/fnins.2022.932270 SN - 1662-4548 VL - Vol. 16 SP - 1 EP - 16 ER - TY - GEN A1 - Glukhov, Artem A1 - Lepri, Nicola A1 - Milo, Valerio A1 - Baroni, Andrea A1 - Zambelli, Cristian A1 - Olivo, Piero A1 - Perez, Eduardo A1 - Wenger, Christian A1 - Ielmini, Daniele T1 - End-to-end modeling of variability-aware neural networks based on resistive-switching memory arrays T2 - Proc. 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2022) N2 - Resistive-switching random access memory (RRAM) is a promising technology that enables advanced applications in the field of in-memory computing (IMC). By operating the memory array in the analogue domain, RRAM-based IMC architectures can dramatically improve the energy efficiency of deep neural networks (DNNs). However, achieving a high inference accuracy is challenged by significant variation of RRAM conductance levels, which can be compensated by (i) advanced programming techniques and (ii) variability-aware training (VAT) algorithms. In both cases, however, detailed knowledge and accurate physics-based statistical models of RRAM are needed to develop programming and VAT methodologies. This work presents an end-to-end approach to the development of highly-accurate IMC circuits with RRAM, encompassing the device modeling, the precise programming algorithm, and the VAT simulations to maximize the DNN classification accuracy in presence of conductance variations. KW - RRAM KW - HfO2 KW - neural network KW - memristive switching Y1 - 2022 U6 - https://doi.org/10.1109/VLSI-SoC54400.2022.9939653 SP - 1 EP - 5 ER - TY - GEN A1 - Glukhov, Artem A1 - Milo, Valerio A1 - Baroni, Andrea A1 - Lepri, Nicola A1 - Zambelli, Cristian A1 - Olivo, Piero A1 - Perez, Eduardo A1 - Wenger, Christian A1 - Ielmini, Daniele T1 - Statistical model of program/verify algorithms in resistive-switching memories for in-memory neural network accelerators T2 - 2022 IEEE International Reliability Physics Symposium (IRPS) N2 - Resistive-switching random access memory (RRAM) is a promising technology for in-memory computing (IMC) to accelerate training and inference of deep neural networks (DNNs). This work presents the first physics-based statistical model describing (i) multilevel RRAM device program/verify (PV) algorithms by controlled set transition, (ii) the stochastic cycle-to-cycle (C2C) and device-to-device (D2D) variations within the array, and (iii) the impact of such imprecisions on the accuracy of DNN accelerators. The model can handle the full chain from RRAM materials/device parameters to the DNN performance, thus providing a valuable tool for device/circuit codesign of hardware DNN accelerators. KW - RRAM KW - Multilevel switching KW - neural network Y1 - 2022 SN - 978-1-6654-7950-9 SN - 978-1-6654-7951-6 U6 - https://doi.org/10.1109/IRPS48227.2022.9764497 SN - 2473-2001 SP - 3C.3-1 EP - 3C.3-7 PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Baroni, Andrea A1 - Glukhov, Artem A1 - Perez, Eduardo A1 - Wenger, Christian A1 - Ielmini, Daniele A1 - Olivo, Piero A1 - Zambelli, Cristian T1 - Low Conductance State Drift Characterization and Mitigation in Resistive Switching Memories (RRAM) for Artificial Neural Networks T2 - IEEE Transactions on Device and Materials Reliability N2 - The crossbar structure of Resistive-switching random access memory (RRAM) arrays enabled the In-Memory Computing circuits paradigm, since they imply the native acceleration of a crucial operations in this scenario, namely the Matrix-Vector-Multiplication (MVM). However, RRAM arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation. A critical one is related to the drift of the low conductance states appearing immediately at the end of program and verify algorithms that are mandatory for an accurate multi-level conductance operation. In this work, we analyze the benefits of a new programming algorithm that embodies Set and Reset switching operations to achieve better conductance control and lower variability. Data retention analysis performed with different temperatures for 168 hours evidence its superior performance with respect to standard programming approach. Finally, we explored the benefits of using our methodology at a higher abstraction level, through the simulation of an Artificial Neural Network for image recognition task (MNIST dataset). The accuracy achieved shows higher performance stability over temperature and time. KW - RRAM KW - neural network KW - Multilevel switching Y1 - 2022 U6 - https://doi.org/10.1109/TDMR.2022.3182133 SN - 1530-4388 VL - 22 IS - 3 SP - 340 EP - 347 ER - TY - GEN A1 - Baroni, Andrea A1 - Zambelli, Cristian A1 - Olivo, Piero A1 - Perez, Eduardo A1 - Wenger, Christian A1 - Ielmini, Daniele T1 - Tackling the Low Conductance State Drift through Incremental Reset and Verify in RRAM Arrays T2 - 2021 IEEE International Integrated Reliability Workshop (IIRW), South Lake Tahoe, CA, USA, 10 December 2021 N2 - Resistive switching memory (RRAM) is a promising technology for highly efficient computing scenarios. RRAM arrays enabled the acceleration of neural networks for artificial intelligence and the creation of In-Memory Computing circuits. However, the arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation in those applications. Among those, one is related to the drift of the low conductance states appearing immediately at the end of program and verify algorithms that are fundamental for an accurate Multi-level conductance operation. In this work, we tackle the issue by developing an Incremental Reset and Verify technique showing enhanced variability and reliability features compared with a traditional refresh-based approach. KW - RRAM KW - resistive switching KW - neural network Y1 - 2021 SN - 978-1-6654-1794-5 SN - 978-1-6654-1795-2 U6 - https://doi.org/10.1109/IIRW53245.2021.9635613 SN - 2374-8036 PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Milo, Valerio A1 - Anzalone, Francesco A1 - Zambelli, Cristian A1 - Perez, Eduardo A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Ossorio, Óscar G. A1 - Olivo, Piero A1 - Wenger, Christian A1 - Ielmini, Daniele T1 - Optimized programming algorithms for multilevel RRAM in hardware neural networks T2 - IEEE International Reliability Physics Symposium (IRPS), 2021 N2 - A key requirement for RRAM in neural network accelerators with a large number of synaptic parameters is the multilevel programming. This is hindered by resistance imprecision due to cycle-to-cycle and device-to-device variations. Here, we compare two multilevel programming algorithms to minimize resistance variations in a 4-kbit array of HfO 2 RRAM. We show that gate-based algorithms have the highest reliability. The optimized scheme is used to implement a neural network with 9-level weights, achieving 91.5% (vs. software 93.27%) in MNIST recognition. KW - RRAM KW - Multilevel switching KW - neural network KW - memristive switching Y1 - 2021 SN - 978-1-7281-6894-4 U6 - https://doi.org/10.1109/IRPS46558.2021.9405119 SN - 1938-1891 ER - TY - GEN A1 - Grossi, Alessandro A1 - Walczyk, Damian A1 - Zambelli, Cristian A1 - Miranda, Enrique A1 - Olivo, Piero A1 - Stikanov, V. A1 - Feriani, A. A1 - Sune, J. A1 - Schoof, Gunther A1 - Kraemer, Rolf A1 - Tillack, Bernd A1 - Fox, A. A1 - Schroeder, Thomas A1 - Walczyk, Christian T1 - Impact of Intercell and Intracell Variability on Forming and Switching Parameters in RRAM Arrays T2 - IEEE Transaction on Electronic Devices Y1 - 2015 U6 - https://doi.org/10.1109/TED.2015.2442412 SN - 0018-9383 VL - 62 IS - 8 SP - 2502 EP - 2509 ER - TY - GEN A1 - Reiser, Daniel A1 - Reichenbach, Marc A1 - Rizzi, Tommaso A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Wenger, Christian A1 - Zambelli, Cristian A1 - Bertozzi, Davide T1 - Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations T2 - 21st IEEE Interregional NEWCAS Conference (NEWCAS), 26-28 June 2023, Edinburgh, United Kingdom N2 - In-memory computing with resistive-switching random access memory (RRAM) crossbar arrays has the potential to overcome the major bottlenecks faced by digital hardware for data-heavy workloads such as deep learning. However, RRAM devices are subject to several non-idealities that result in significant inference accuracy drops compared with software baseline accuracy. A critical one is related to the drift of the conductance states appearing immediately at the end of program and verify algorithms that are mandatory for accurate multi-level conductance operation. The support of drift models in state-of-the-art simulation tools of memristive computationin-memory is currently only in the early stage, since they overlook key device- and array-level parameters affecting drift resilience such as the programming algorithm of RRAM cells, the choice of target conductance states and the weight-toconductance mapping scheme. The goal of this paper is to fully expose these parameters to RRAM crossbar designers as a multi-dimensional optimization space of drift resilience. For this purpose, a simulation framework is developed, which comes with the suitable abstractions to propagate the effects of those RRAM crossbar configuration parameters to their ultimate implications over inference performance stability. KW - RRAM Y1 - 2023 SN - 979-8-3503-0024-6 SN - 979-8-3503-0025-3 U6 - https://doi.org/10.1109/NEWCAS57931.2023 PB - IEEE CY - Piscataway, NJ ER -