TY - GEN
A1 - Perez-Bosch Quesada, Emilio
A1 - Mistroni, Alberto
A1 - Jia, Ruolan
A1 - Dorai Swamy Reddy, Keerthi
A1 - Reichmann, Felix
A1 - Castan, Helena
A1 - Dueñas, Salvador
A1 - Wenger, Christian
A1 - Perez, Eduardo
T1 - Forming and resistive switching of HfO₂-based RRAM devices at cryogenic temperature
T2 - IEEE Electron Device Letters
N2 - Reliable data storage technologies able to operate at cryogenic temperatures are critical to implement scalable quantum computers and develop deep-space exploration systems, among other applications. Their scarce availability is pushing towards the development of emerging memories that can perform such storage in a non-volatile fashion. Resistive Random-Access Memories (RRAM) have demonstrated their switching capabilities down to 4K. However, their operability at lower temperatures still remain as a challenge. In this work, we demonstrate for the first time the forming and resistive switching capabilities of CMOS-compatible RRAM devices at 1.4K. The HfO2-based devices are deployed following an array of 1-transistor-1-resistor (1T1R) cells. Their switching performance at 1.4K was also tested in the multilevel-cell (MLC) approach, storing up to 4 resistance levels per cell.
KW - RRAM
Y1 - 2024
U6 - https://doi.org/10.1109/LED.2024.3485873
SN - 0741-3106
VL - 45
IS - 12
SP - 2391
EP - 2394
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -
TY - GEN
A1 - Weißhaupt, David
A1 - Sürgers, Christoph
A1 - Bloos, Dominik
A1 - Funk, Hannes Simon
A1 - Oehme, Michael
A1 - Fischer, Gerda
A1 - Schubert, Markus Andreas
A1 - Wenger, Christian
A1 - van Slageren, Joris
A1 - Fischer, Inga Anita
A1 - Schulze, Jörg
T1 - Lateral Mn5Ge3 spin-valve in contact with a high-mobility Ge two-dimensional hole gas
T2 - Semiconductor Science and Technology
N2 - Abstract
Ge two-dimensional hole gases (2DHG) in strained modulation-doped quantum-wells represent a promising material platform for future spintronic applications due to their excellent spin transport properties and the theoretical possibility of efficient spin manipulation. Due to the continuous development of epitaxial growth recipes extreme high hole mobilities and low effective masses can be achieved, promising an efficient spin transport. Furthermore, the Ge 2DHG can be integrated in the well-established industrial complementary metal-oxide-semiconductor (CMOS) devices technology. However, efficient electrical spin injection into a Ge 2DHG—an essential prerequisite for the realization of spintronic devices—has not yet been demonstrated. In this work, we report the fabrication and low-temperature magnetoresistance (MR) measurements of a laterally structured Mn5Ge3/Ge 2DHG/ Mn5Ge3 device. The ferromagnetic Mn5Ge3 contacts are grown directly into the Ge quantum well by means of an interdiffusion process with a spacing of approximately 130 nm, forming a direct electrical contact between the ferromagnetic metal and the Ge 2DHG. Here, we report for the first time a clear MR signal for temperatures below 13 K possibly arising from successful spin injection into the high mobility Ge 2DHG. The results represent a step forward toward the realization of CMOS compatible spintronic devices based on a 2DHG.
KW - two-dimensional hole gas
Y1 - 2024
U6 - https://doi.org/10.1088/1361-6641/ad8d06
SN - 0268-1242
VL - 39
IS - 12
SP - 1
EP - 10
PB - IOP Publishing
ER -
TY - GEN
A1 - Capista, Daniele
A1 - Lukose, Rasuole
A1 - Majnoon, Farnaz
A1 - Lisker, Marco
A1 - Wenger, Christian
A1 - Lukosius, Mindaugas
T1 - Optimization of the metal deposition process for the accurate estimation of Low Metal-Graphene Contact-Resistance
T2 - 47th MIPRO ICT and Electronics Convention (MIPRO), 20-24 May 2024, Opatija, Croatia
Y1 - 2024
SN - 979-8-3503-8250-1
SN - 979-8-3503-8249-5
U6 - https://doi.org/10.1109/MIPRO60963.2024.10569895
SN - 2623-8764
ER -
TY - GEN
A1 - Maldonado, David
A1 - Cantudo, Antonio
A1 - Swamy Reddy, Keerthi Dorai
A1 - Pechmann, Stefan
A1 - Uhlmann, Max
A1 - Wenger, Christian
A1 - Roldan, Juan Bautista
A1 - Pérez, Eduardo
T1 - Influence of stop and gate voltage on resistive switching of 1T1R HfO2-based memristors, a modeling and variability analysis
T2 - Materials Science in Semiconductor Processing
Y1 - 2024
U6 - https://doi.org/10.1016/j.mssp.2024.108726
SN - 1873-4081
SN - 1369-8001
VL - 182
ER -
TY - GEN
A1 - Kosto, Yuliia
A1 - Tschammer, Rudi
A1 - Morales, Carlos
A1 - Henkel, Karsten
A1 - Flege, Jan Ingo
A1 - Ratzke, Markus
A1 - Fischer, Inga Anita
A1 - Costina, Ioan
A1 - Alvarado Chavarin, Carlos
A1 - Wenger, Christian
T1 - Rational design and development of room temperature hydrogen sensors compatible with CMOS technology: a necessary step for the coming renewable hydrogen economy
T2 - Proceedings of iCampus Conference Cottbus 2024
N2 - The transition towards a new, renewable energy system based on green energy vectors, such as hydrogen, requires not only direct energy conversion and storage systems, but also the development of auxiliary components, such as highly sensitive hydrogen gas sensors integrated into mass devices that operate at ambient conditions. Despite the recent advances in nanostructured metal oxide thin films in terms of simple fabrication processes and compatibility with integrated circuits, high sensitivity, and short response/recovery times usually require the use of expensive noble metals or elevated tem-peratures (>250 ºC), which results in high power consumption and poor long-term stability. This article presents the first steps of the work on developing a novel resistive hydrogen gas sensor based on ultrathin cerium oxide films, compatible with complementary metal oxide semiconductor technology and capable of operating at room temperature. Here, we show a multidisciplinary bottom-up approach combining different work areas for the sensor development, such as sensor architecture, sensing mechanism and deposition strategy of the active layer, electrical contact design depending on the desired electrical output, and fast testing under controlled environments.
KW - gas sensors
KW - micro-structering
KW - atomic layer deposition
KW - sensor platform
Y1 - 2024
SN - 978-3-910600-00-3
U6 - https://doi.org/10.5162/iCCC2024/P21
SP - 182
EP - 185
PB - AMA Service GmbH
CY - Wunstorf
ER -
TY - GEN
A1 - Vinuesa, Guillermo
A1 - García, Héctor
A1 - Pérez, Eduardo
A1 - Wenger, Christian
A1 - Íñiguez de la Torre, Ignacio
A1 - González, Tomás
A1 - Dueñas, Salvador
A1 - Castán, Helena
T1 - On the asymmetry of Resistive Switching Transitions
T2 - Electronics
N2 - In this study, the resistive switching phenomena in TiN/Ti/HfO2/Ti metal–insulator–metal stacks is investigated, mainly focusing on the analysis of set and reset transitions. The electrical measurements in a wide temperature range reveal that the switching transitions require less voltage (and thus, less energy) as temperature rises, with the reset process being much more temperature sensitive. The main conduction mechanism in both resistance states is Space-charge-limited Conduction, but the high conductivity state also shows Schottky emission, explaining its temperature dependence. Moreover, the temporal evolution of these transitions reveals clear differences between them, as their current transient response is completely different. While the set is sudden, the reset process development is clearly non-linear, closely resembling a sigmoid function. This asymmetry between switching processes is of extreme importance in the manipulation and control of the multi-level characteristics and has clear implications in the possible applications of resistive switching devices in neuromorphic computing.
KW - resistive switching
KW - RRAM
KW - memristor
KW - transient
KW - temperature dependence
KW - low power consumption
Y1 - 2024
U6 - https://doi.org/10.3390/electronics13132639
SN - 2079-9292
VL - 13
IS - 13
PB - MDPI
ER -
TY - GEN
A1 - Strobel, Carsten
A1 - Alvarado Chavarin, Carlos
A1 - Knaut, Martin
A1 - Albert, Matthias
A1 - Heinzig, André
A1 - Gummadi, Likhith
A1 - Wenger, Christian
A1 - Mikolajick, Thomas
ED - Giannazzo, Filippo
ED - Agnello, Simonpietro
ED - Seravalli, Luca
ED - Bondino, Federica
T1 - p-Type Schottky contacts for graphene adjustable-Barrier phototransistors
T2 - Nanomaterials
N2 - The graphene adjustable-barriers phototransistor is an attractive novel device for potential high speed and high responsivity dual-band photodetection. In this device, graphene is embedded between the semiconductors silicon and germanium. Both n-type and p-type Schottky contacts between graphene and the semiconductors are required for this device. While n-type Schottky contacts are widely investigated, reports about p-type Schottky contacts between graphene and the two involved semiconductors are scarce. In this study, we demonstrate a p-type Schottky contact between graphene and p-germanium. A clear rectification with on–off ratios of close to 10 3 (±5 V) and a distinct photoresponse at telecommunication wavelengths in the infrared are achieved. Further, p-type silicon is transferred to or deposited on graphene, and we also observe rectification and photoresponse in the visible range for some of these p-type Schottky junctions. These results are an important step toward the realization of functional graphene adjustable-barrier phototransistors.
KW - phototransistor
KW - GABT
KW - graphene
KW - p-type
KW - silicon
KW - germanium
KW - high responsivity
KW - high speed
KW - dual-band
KW - photodetection
Y1 - 2024
U6 - https://doi.org/10.3390/nano14131140
SN - 2079-4991
VL - 14
IS - 13
PB - MDPI
ER -
TY - GEN
A1 - Morales, Carlos
A1 - Plate, Paul
A1 - Marth, Ludwig
A1 - Naumann, Franziska
A1 - Kot, Małgorzata
A1 - Janowitz, Christoph
A1 - Kus, Peter
A1 - Zöllner, Marvin Hartwig
A1 - Wenger, Christian
A1 - Henkel, Karsten
A1 - Flege, Jan Ingo
T1 - Bottom-up design of a supercycle recipe for atomic layer deposition of tunable Indium Gallium Zinc Oxide thin films
T2 - ACS Applied Electronic Materials
N2 - We present a successful bottom-up approach to design a generic plasma-enhanced atomic layer deposition (PEALD) supercycle recipe to grow high-quality indium gallium zinc oxide (IGZO) thin films with tunable composition at a relatively low temperature of 150 °C. In situ real-time ellipsometric characterization in combination with ex situ complementary techniques has been used to optimize the deposition process and quality of the films by identifying and solving growth challenges such as degree of oxidation, nucleation delays, or elemental composition. The developed supercycle approach enables facile control of the target composition by adapting the subcycle ratios within the supercycle process. Compared to other low-temperature deposition techniques resulting in amorphous films, our PEALD–IGZO process at 150 °C results in nearly amorphous, nanocrystalline films. The preparation of IGZO films at low temperature by a supercycle PEALD approach allows controlling the thickness, composition, and electrical properties while preventing thermally induced segregation.
KW - IGZO
KW - PEALD
KW - supercycle
KW - XPS depth profiling
KW - current density
Y1 - 2024
U6 - https://doi.org/10.1021/acsaelm.4c00730
SN - 2637-6113
VL - 6
IS - 8
SP - 5694
EP - 5704
PB - American Chemical Society (ACS)
ER -
TY - GEN
A1 - Hayat, Ahsan
A1 - Ratzke, Markus
A1 - Alvarado Chavarin, Carlos
A1 - Zöllner, Marvin Hartwig
A1 - Corley-Wiciak, Agnieszka Anna
A1 - Schubert, Markus Andreas
A1 - Wenger, Christian
A1 - Fischer, Inga Anita
T1 - Structural and morphological properties of CeO2 films deposited by radio frequency magnetron sputtering for back-end-of-line integration
T2 - Thin Solid Films
Y1 - 2024
U6 - https://doi.org/10.1016/j.tsf.2024.140547
SN - 0040-6090
VL - 807
ER -
TY - GEN
A1 - Fritscher, Markus
A1 - Singh, Simranjeet
A1 - Rizzi, Tommaso
A1 - Baroni, Andrea
A1 - Reiser, Daniel
A1 - Mallah, Maen
A1 - Hartmann, David
A1 - Bende, Ankit
A1 - Kempen, Tim
A1 - Uhlmann, Max
A1 - Kahmen, Gerhard
A1 - Fey, Dietmar
A1 - Rana, Vikas
A1 - Menzel, Stephan
A1 - Reichenbach, Marc
A1 - Krstic, Milos
A1 - Merchant, Farhad
A1 - Wenger, Christian
T1 - A flexible and fast digital twin for RRAM systems applied for training resilient neural networks
T2 - Scientific Reports
N2 - Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the “ideal memristor” which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a “push button” modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).
KW - RRAM
KW - Neural network
KW - digital twin
Y1 - 2024
U6 - https://doi.org/10.1038/s41598-024-73439-z
SN - 2045-2322
VL - 14
IS - 1
PB - Springer Science and Business Media LLC
ER -
TY - GEN
A1 - Lukosius, Mindaugas
A1 - Lukose, Rasuolė
A1 - Dubey, P. K.
A1 - Raju, A. I.
A1 - Capista, Daniele
A1 - Lisker, Marco
A1 - Mai, A.
A1 - Wenger, Christian
T1 - Graphene for photonic applications
T2 - 2024 47th MIPRO ICT and Electronics Convention (MIPRO)
N2 - Integrating graphene into Silicon Complementary Metal-Oxide-Semiconductor (CMOS) technology for photonic applications holds immense promise, but it encounters challenges in establishing large-scale graphene processes. These challenges encompass growth through techniques like Chemical Vapor Deposition (CVD), transfer, encapsulation, and contact formation within a routine 200mm wafer pilot line typically utilized for integrated circuit fabrication. This study is dedicated to exploring various facets of graphene research within a 200 mm pilot line, with a focus on overcoming challenges through the fabrication of proof-of-concept photonic graphene-based devices. The synthesis of graphene targeted epi-Ge(100)/Si(100) substrates, grown within the IHP pilot line, showcasing the potential for high-quality graphene deposition across 200mm wafers. Alternatively, employing different orientations such as (110) has been explored to enhance graphene mobility, achieving a remarkable mobility of 2300 cm 2 /Vs at present. The study systematically investigates graphene quality, thickness, and homogeneity utilizing techniques such as Raman spectroscopy, Atomic Force Microscopy (AFM), and Scanning Electron Microscopy (SEM). Additionally, simulations and fabrication of the graphene ring modulators have been conducted at both the component and device levels, incorporating realistic graphene properties. These results indicate a modulation depth of 1.6 dB/μm and a 3dB bandwidth of 7 GHz, showcasing the potential of graphene-based photonic devices for high-speed communication applications.
KW - Graphene
Y1 - 2024
SN - 979-8-3503-8250-1
SN - 979-8-3503-8249-5
U6 - https://doi.org/10.1109/MIPRO60963.2024.10569652
SN - 2623-8764
SP - 1614
EP - 1618
PB - IEEE
ER -
TY - GEN
A1 - Fritscher, Markus
A1 - Wenger, Christian
A1 - Krstic, Milos
T1 - From device to application - integrating RRAM Accelerator Blocks into large AI systems
T2 - 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
N2 - This work provides an introduction to design methodologies for RRAM-based systems. We illustrate the impact of device variation on the performance of neural networks and propose a circuit-level integration approach for RRAM-based compute blocks. Moreover, we demonstrate a possible architectural integration by incorporating RRAM-based VMM blocks fabricated in a 130 nm CMOS process into a RISC-V.
KW - RRAM
Y1 - 2024
SN - 979-8-3503-5411-9
SN - 979-8-3503-5412-6
U6 - https://doi.org/10.1109/ISVLSI61997.2024.00111
SN - 2159-3477
SP - 592
EP - 592
PB - IEEE
ER -
TY - GEN
A1 - Fritscher, Markus
A1 - Uhlmann, Max
A1 - Ostrovskyy, Philip
A1 - Reiser, Daniel
A1 - Chen, Junchao
A1 - Schubert, Andreas
A1 - Schulze, Carsten
A1 - Kahmen, Gerhard
A1 - Fey, Dietmar
A1 - Reichenbach, Marc
A1 - Krstic, Milos
A1 - Wenger, Christian
T1 - Area-efficient digital design using RRAM-CMOS standard cells
T2 - 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
N2 - Extending the scalability of digital integrated circuits through novel device concepts is an attractive option. Among these concepts, resistive random access memory (RRAM) devices allow fast and nonvolatile operation. However, building large memristive systems is still challenging since large analog circuits have to be designed and integrated. In this paper, we propose a novel solution - the implementation of digital standard cells by the means of RRAM devices. While this methodology is universal, with applications ranging from few-device-circuits to large macroblocks, we demonstrate it for a 2T2R-cell. The benefits of using RRAM devices are demonstrated by implementing a NAND standard cell merely consuming the area of two transistors. This cell is about 25 % smaller than the equivalent CMOS NAND in the same technology. We use these cells to implement a half adder, beating the area of the equivalent CMOS implementation using more sophisticates gates by 15 %. Lastly, we fully integrate this novel standard cell into a digital standard cell library and perform a synthesis and layout of a RISC-V CPU core.
KW - RRAM
Y1 - 2024
SN - 979-8-3503-5411-9
SN - 979-8-3503-5412-6
U6 - https://doi.org/10.1109/ISVLSI61997.2024.00026
SN - 2159-3477
VL - 18
SP - 81
EP - 87
PB - IEEE
ER -
TY - GEN
A1 - Vinuesa, Guillermo
A1 - Garcia, Hector
A1 - Duenas, Salvador
A1 - Castan, Helena
A1 - Iñiguez de la Torre, Ignacio
A1 - Gonzalez, Tomas
A1 - Dorai Swamy Reddy, Keerthi
A1 - Uhlmann, Max
A1 - Wenger, Christian
A1 - Perez, Eduardo
T1 - Effect of the temperature on the performance and dynamic behavior of HfO2-Based Rram Devices
T2 - ECS Meeting Abstracts
N2 - Over the past decades, the demand for semiconductor memory devices has been steadily increasing, and is currently experiencing an unprecedented boost due to the development and expansion of artificial intelligence. Among emerging high-density non-volatile memories, resistive random-access memory (RRAM) is one of the best recourses for all kind of applications, such as neuromorphic computing or hardware security [1]. Although many materials have been evaluated for RRAM development, some of them with excellent results, HfO2 is one of the established materials in CMOS domain due to its compatibility with standard materials and processes [2].
The main goal of this work is to study the switching capability and stability of HfO2-based RRAMs, as well as to explore their ability in the field of analogue applications, by analyzing the evolution of the resistance states that allow multilevel control. Indeed, analogue operation is a key point for achieving electronic neural synapses in neuromorphic systems, with synaptic weight information encoded in the different resistance states. This research has been carried out over a wide temperature range, between 40 and 340 K, as we are interested in testing the extent to which performance is maintained or modified, with a view to designing neuromorphic circuits that are also suitable in the low-temperature realm. We aim to prove that these simple, fast, high integration density structures can also be used in circuits designed for specific applications, such as aerospace systems.
The RRAM devices studied in this work are TiN/Ti/8 nm-HfO2/TiN metal-insulator-metal (MIM) capacitors. Dielectric layers were atomic layer deposited (ALD). It has been demonstrated that the Ti coat in the top electrode acts as a scavenger that absorbs oxygen atoms from the HfO2 layer, and facilitates the creation of conductive filaments of oxygen vacancies [3]. In fact, the oxygen reservoir capability of Ti is well known, as it is able to attract and release oxygen atoms from or to the HfO2 layer during the RRAM operation [4]. The clustering of vacancies extends through the entire thickness of the oxide and, after an electroformig step, it joins the upper and lower electrodes and the device reaches the low resistance state (LRS). By applying adequate electrical signals, the filaments can be partially dissolved, which brings the device into the high-resistance state (HRS), with lower current values. The set process brings the device to the LRS state, while the reset one brings it to the HRS. The dependence of electrical conductivity on external applied electrical excitation allows triggering the device between the both states in a non-volatile manner [5].
The experimental equipment used consisted of a Keithley 4200-SCS semiconductor parameter analyzer and a Lake Shore cryogenic probe station. Fig.1 shows current-voltage cycles measured at different temperatures; the averages values at each temperature, both in logarithmic and linear scale, are also shown. The functional window increases as temperature decreases.
The evolutions of set and reset voltage values with temperature are depicted in Fig.2, whereas the current values (measured at 0.1 V) corresponding to the LRS and HRS can be seen in Fig.3. LRS resistance decreases as temperature increases, in agreement with semiconductor behaviour, probably due to a hopping conduction mechanism. Both set and reset voltages decrease as temperature increases; the reset process is smoother at high temperatures. The reduction in reset voltage variability as temperature increases is very notable.
Finally, Fig. 4 shows a picture of the transient behaviour; in the right panel of the same figure, the amplitudes of the current transients in the reset state have been included in the external loop.
To sum up, the resistive switching phenomena is studied in a wide temperature range. The LRS shows semiconducting behavior with temperature, most likely related to a hopping conduction mechanism. Switching voltages decrease as temperature increases, with a notable reduction in reset voltage variability. An excellent control of intermediate resistance state is shown through current transients at several voltages in the reset process.
REFERENCES
[1] M. Asif et al., Materials Today Electronics 1, 100004 (2022).
[2] S. Slesazeck et al., Nanotechnology 30, 352003 (2019).
[3] Z. Fang et al., IEEE Electron Device Letters 35, 9, 912-914 (2014).
[4] H. Y. Lee et al., IEEE Electron Device Letters 31, 1, 44-46 (2010).
[5] D. J. Wouters et al., Proceedings of the IEEE 103, 8, 1274-1288 (2015).
Figure 1
KW - RRAM
Y1 - 2024
U6 - https://doi.org/10.1149/MA2024-01211297mtgabs
SN - 2151-2043
VL - MA2024-01
IS - 21
SP - 1297
EP - 1297
PB - The Electrochemical Society
ER -
TY - GEN
A1 - Wen, Jianan
A1 - Baroni, Andrea
A1 - Perez, Eduardo
A1 - Uhlmann, Max
A1 - Fritscher, Markus
A1 - KrishneGowda, Karthik
A1 - Ulbricht, Markus
A1 - Wenger, Christian
A1 - Krstic, Milos
T1 - Towards reliable and energy-efficient RRAM based discrete fourier transform accelerator
T2 - 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)
N2 - The Discrete Fourier Transform (DFT) holds a prominent place in the field of signal processing. The development of DFT accelerators in edge devices requires high energy efficiency due to the limited battery capacity. In this context, emerging devices such as resistive RAM (RRAM) provide a promising solution. They enable the design of high-density crossbar arrays and facilitate massively parallel and in situ computations within memory. However, the reliability and performance of the RRAM-based systems are compromised by the device non-idealities, especially when executing DFT computations that demand high precision. In this paper, we propose a novel adaptive variability-aware crossbar mapping scheme to address the computational errors caused by the device variability. To quantitatively assess the impact of variability in a communication scenario, we implemented an end-to-end simulation framework integrating the modulation and demodulation schemes. When combining the presented mapping scheme with an optimized architecture to compute DFT and inverse DFT(IDFT), compared to the state-of-the-art architecture, our simulation results demonstrate energy and area savings of up to 57 % and 18 %, respectively. Meanwhile, the DFT matrix mapping error is reduced by 83% compared to conventional mapping. In a case study involving 16-quadrature amplitude modulation (QAM), with the optimized architecture prioritizing energy efficiency, we observed a bit error rate (BER) reduction from 1.6e-2 to 7.3e-5. As for the conventional architecture, the BER is optimized from 2.9e-3 to zero.
KW - RRAM
Y1 - 2024
SN - 978-3-9819263-8-5
SN - 979-8-3503-4860-6
U6 - https://doi.org/10.23919/DATE58400.2024.10546709
SN - 1558-1101
SP - 1
EP - 6
PB - IEEE
ER -
TY - GEN
A1 - Maldonado, David
A1 - Baroni, Andrea
A1 - Aldana, Samuel
A1 - Dorai Swamy Reddy, Keerthi
A1 - Pechmann, Stefan
A1 - Wenger, Christian
A1 - Roldán, Juan Bautista
A1 - Pérez, Eduardo
T1 - Kinetic Monte Carlo simulation analysis of the conductance drift in Multilevel HfO2-based RRAM devices
T2 - Nanoscale
N2 - The drift characteristics of valence change memory (VCM) devices have been analyzed through both experimental analysis and 3D kinetic Monte Carlo (kMC) simulations.
KW - RRAM
Y1 - 2024
U6 - https://doi.org/10.1039/d4nr02975e
SN - 2040-3364
VL - 16
IS - 40
SP - 19021
EP - 19033
PB - Royal Society of Chemistry (RSC)
ER -
TY - GEN
A1 - Uhlmann, Max
A1 - Rizzi, Tommaso
A1 - Wen, Jianan
A1 - Pérez-Bosch Quesada, Emilio
A1 - Al Beattie, Bakr
A1 - Ochs, Karlheinz
A1 - Pérez, Eduardo
A1 - Ostrovskyy, Philip
A1 - Carta, Corrado
A1 - Wenger, Christian
A1 - Kahmen, Gerhard
T1 - LUT-based RRAM model for neural accelerator circuit simulation
T2 - Proceedings of the 18th ACM International Symposium on Nanoscale Architectures
N2 - Neural hardware accelerators have been proven to be energy-efficient when used to solve tasks which can be mapped into an artificial neural network (ANN) structure. Resistive random-access memories (RRAMs) are currently under investigation together with several different memristive devices as promising technologies to build such accelerators combined together with complementary metal-oxide semiconductor (CMOS)-technologies in integrated circuits (ICs). While many research groups are actively developing sophisticated physical-based representations to better understand the underlying phenomena characterizing these devices, not much work has been dedicated to exploit the trade-off between simulation time and accuracy in the definition of low computational demanding models suitable to be used at many abstraction layers. Indeed, the design of complex mixed-signal systems as a neural hardware accelerators requires frequent interaction between the application- and the circuit-level that can be enabled only with the support of accurate and fast-simulating devices’ models. In this work, we propose a solution to fill the aforementioned gap with a lookup table (LUT)-based Verilog-A model of IHP’s 1-transistor-1-RRAM (1T1R) cell. In addition, the implementation challenges of conveying the communication between the abstract ANN simulation and the circuital analysis are tackled with a design flow for resistive neural hardware accelerators that features a custom Python wrapper. As a demonstration of the proposed design flow and 1T1R model, an ANN for the MNIST handwritten digit recognition task is assessed with the last layer verified in circuit simulation. The obtained recognition confidence intervals show a considerable discrepancy between the purely application-level PyTorch simulation and the proposed design flow which spans across the abstraction layers down to the circuital analysis.
KW - RRAM
KW - Neural network
Y1 - 2023
U6 - https://doi.org/10.1145/3611315.3633273
SP - 1
EP - 6
PB - ACM
CY - New York, NY, USA
ER -
TY - GEN
A1 - Strobel, Carsten
A1 - Alvarado Chavarin, Carlos
A1 - Völkel, Sandra
A1 - Jahn, Andreas
A1 - Hiess, Andre
A1 - Knaut, Martin
A1 - Albert, Matthias
A1 - Wenger, Christian
A1 - Steinke, Olaff
A1 - Stephan, Ulf
A1 - Röhlecke, Sören
A1 - Mikolajick, Thomas
T1 - Enhanced Electrical Properties of Optimized Vertical Graphene-Base Hot Electron Transistors
T2 - ACS Applied Electronic Materials
N2 - The arrival of high-mobility two-dimensional materials like graphene leads to the renaissance of former vertical semiconductor–metal–semiconductor (SMS) hot electron transistors. Because of the monolayer thickness of graphene, improved SMS transistors with a semimetallic graphene-base electrode are now feasible for high-frequency applications. In this study we report about a device that consists of amorphous silicon, graphene, and crystalline silicon. For the first time, this device is fabricated by a four-mask lithography process which leads to significant improvements in the device performance. A strongly increased common-emitter current gain of 2% could be achieved while the on–off ratio improved to 1.6 × 105, which is already higher than predicted theoretically. This could be mainly attributed to better interface characteristics and decreased lateral dimensions of the devices. A cutoff frequency of approximately 26 MHz could be forecasted based on the DC measurements of the device.
KW - Graphene
KW - Transistor
Y1 - 2023
U6 - https://doi.org/10.1021/acsaelm.2c01725
SN - 2637-6113
VL - 5
IS - 3
SP - 1670
EP - 1675
ER -