TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Perez, Eduardo A1 - Uhlmann, Max A1 - Fritscher, Markus A1 - KrishneGowda, Karthik A1 - Ulbricht, Markus A1 - Wenger, Christian A1 - Krstic, Milos T1 - Towards reliable and energy-efficient RRAM based discrete fourier transform accelerator T2 - 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) N2 - The Discrete Fourier Transform (DFT) holds a prominent place in the field of signal processing. The development of DFT accelerators in edge devices requires high energy efficiency due to the limited battery capacity. In this context, emerging devices such as resistive RAM (RRAM) provide a promising solution. They enable the design of high-density crossbar arrays and facilitate massively parallel and in situ computations within memory. However, the reliability and performance of the RRAM-based systems are compromised by the device non-idealities, especially when executing DFT computations that demand high precision. In this paper, we propose a novel adaptive variability-aware crossbar mapping scheme to address the computational errors caused by the device variability. To quantitatively assess the impact of variability in a communication scenario, we implemented an end-to-end simulation framework integrating the modulation and demodulation schemes. When combining the presented mapping scheme with an optimized architecture to compute DFT and inverse DFT(IDFT), compared to the state-of-the-art architecture, our simulation results demonstrate energy and area savings of up to 57 % and 18 %, respectively. Meanwhile, the DFT matrix mapping error is reduced by 83% compared to conventional mapping. In a case study involving 16-quadrature amplitude modulation (QAM), with the optimized architecture prioritizing energy efficiency, we observed a bit error rate (BER) reduction from 1.6e-2 to 7.3e-5. As for the conventional architecture, the BER is optimized from 2.9e-3 to zero. KW - RRAM Y1 - 2024 SN - 978-3-9819263-8-5 SN - 979-8-3503-4860-6 U6 - https://doi.org/10.23919/DATE58400.2024.10546709 SN - 1558-1101 SP - 1 EP - 6 PB - IEEE ER - TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Pérez, Eduardo A1 - Ulbricht, Markus A1 - Wenger, Christian A1 - Krstic, Milos T1 - Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages T2 - 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) N2 - RRAM technology is a promising candidate for implementing efficient AI accelerators with extensive multiply-accumulate operations. By scaling RRAM devices to the synaptic crossbar array, the computations can be realized in situ, avoiding frequent weights transfer between the processing units and memory. Besides, as the computations are conducted in the analog domain with high flexibility, applying multilevel input voltages to the RRAM devices with multilevel conductance states enhances the computational efficiency further. However, several non-idealities existing in emerging RRAM technology may degrade the reliability of the system. In this paper, we measured and investigated the impact of read disturb on RRAM devices with different input voltages, which incurs conductance drifts and introduces errors. The measured data are deployed to simulate the RRAM based AI inference engines with multilevel states. KW - RRAM KW - Multilevel switching KW - AI accelarator Y1 - 2022 SN - 978-1-6654-5938-9 SN - 978-1-6654-5937-2 U6 - https://doi.org/10.1109/DFT56152.2022.9962345 SN - 2765-933X SP - 1 EP - 6 ER - TY - GEN A1 - Perez-Bosch Quesada, Emilio A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Rizzi, Tommaso A1 - Wen, Jianan A1 - Ulbricht, Markus A1 - Krstic, Milos A1 - Wenger, Christian A1 - Pérez, Eduardo T1 - Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing T2 - IEEE Transactions on Electron Devices N2 - Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of 8x8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices’ nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems. KW - RRAM KW - Vector Matrix Multiplication KW - variability Y1 - 2023 U6 - https://doi.org/10.1109/TED.2023.3244509 SN - 0018-9383 VL - 70 IS - 4 SP - 2009 EP - 2014 ER -