TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Perez, Eduardo A1 - Uhlmann, Max A1 - Fritscher, Markus A1 - KrishneGowda, Karthik A1 - Ulbricht, Markus A1 - Wenger, Christian A1 - Krstic, Milos T1 - Towards reliable and energy-efficient RRAM based discrete fourier transform accelerator T2 - 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) N2 - The Discrete Fourier Transform (DFT) holds a prominent place in the field of signal processing. The development of DFT accelerators in edge devices requires high energy efficiency due to the limited battery capacity. In this context, emerging devices such as resistive RAM (RRAM) provide a promising solution. They enable the design of high-density crossbar arrays and facilitate massively parallel and in situ computations within memory. However, the reliability and performance of the RRAM-based systems are compromised by the device non-idealities, especially when executing DFT computations that demand high precision. In this paper, we propose a novel adaptive variability-aware crossbar mapping scheme to address the computational errors caused by the device variability. To quantitatively assess the impact of variability in a communication scenario, we implemented an end-to-end simulation framework integrating the modulation and demodulation schemes. When combining the presented mapping scheme with an optimized architecture to compute DFT and inverse DFT(IDFT), compared to the state-of-the-art architecture, our simulation results demonstrate energy and area savings of up to 57 % and 18 %, respectively. Meanwhile, the DFT matrix mapping error is reduced by 83% compared to conventional mapping. In a case study involving 16-quadrature amplitude modulation (QAM), with the optimized architecture prioritizing energy efficiency, we observed a bit error rate (BER) reduction from 1.6e-2 to 7.3e-5. As for the conventional architecture, the BER is optimized from 2.9e-3 to zero. KW - RRAM Y1 - 2024 SN - 978-3-9819263-8-5 SN - 979-8-3503-4860-6 U6 - https://doi.org/10.23919/DATE58400.2024.10546709 SN - 1558-1101 SP - 1 EP - 6 PB - IEEE ER - TY - CHAP A1 - Ulbricht, Markus A1 - Schölzel, Mario A1 - Koal, Tobias A1 - Vierhaus, Heinrich Theodor T1 - A New Hierarchical Built-In Test with On-Chip Diagnosis for VLIW Processors T2 - IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS 2011), Cottbus, Germany, 13 - 15 April 2011 N2 - Tagungsbeitrag DDECS 2011, Cottbus KW - Prozessoren KW - Test KW - Zuverlässigkeit Y1 - 2011 UR - www.computer.org SN - 978-1-4244-9755-3 N1 - IEEE Computer Society SP - 143 EP - 146 ER - TY - CHAP A1 - Ulbricht, Markus A1 - Schölzel, Mario A1 - Koal, Tobias A1 - Vierhaus, Heinrich Theodor T1 - A New Hiararchical Built-In SElf Test with On-Chip Diagnosis for VLIW Processors N2 - Tagungsbeitrag 23. ITG-Tagung "Test und Zuverlässigeit von Schaltungen und Systemen", Passau, 2011 KW - Prozessoren KW - Test KW - Zuverlässigkeit Y1 - 2011 N1 - BTU ER - TY - CHAP A1 - Koal, Tobias A1 - Ulbricht, Markus A1 - Engelke, Piet A1 - Vierhaus, Heinrich Theodor ED - Drechsler, Rolf T1 - Logic Self Repair Architecture with Self Test Capabilities T2 - Zuverlässigkeit und Entwurf, 6. GMM/GI/ITG-Fachtagung vom 25. bis 27. September 2012 in Bremen Y1 - 2012 SN - 978-3-8007-3445-0 PB - VDE-Verl. CY - Berlin [u.a.] ER - TY - CHAP A1 - Koal, Tobias A1 - Ulbricht, Markus A1 - Engelke, Piet A1 - Vierhaus, Heinrich Theodor T1 - Selbstreparatur für Logik-Baugruppen mit erweiterten Fähigkeiten für die Kompensation von Fertigungsfehlern und Frühausfällen T2 - Dresdner Arbeitstagung für Schaltungs- und Systementwurf (DASS), Dresden, Mai 2012, Tagungsband Y1 - 2012 SN - 978-3-8396-0404-5 PB - Fraunhofer IIS, Institutsteil EAS [u.a.] CY - Dresden ER - TY - CHAP A1 - Ulbricht, Markus A1 - Koal, Tobias A1 - Vierhaus, Heinrich Theodor T1 - Activity Migration in M-of-N-Systems by Means of Loading-Balancing T2 - 15th Euromicro Conference on Digital Systems Design (DSD), September 2012 Y1 - 2012 SN - 978-1-4673-2498-4 SP - 258 EP - 263 PB - IEEE CY - Piscataway ER - TY - CHAP A1 - Koal, Tobias A1 - Ulbricht, Markus A1 - Engelke, Piet A1 - Vierhaus, Heinrich Theodor ED - Sekanina, Lukas T1 - On the Feasibility of Combining On-Line-Test and Self Repair for Logic Circuits T2 - 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2013), Karlovny Vary, April 2013 Y1 - 2013 SN - 978-1-4673-6135-4 PB - IEEE Computer Society ER - TY - CHAP A1 - Koal, Tobias A1 - Ulbricht, Markus A1 - Engelke, Piet A1 - Vierhaus, Heinrich Theodor ED - Dietrich, Manfred T1 - On-Line-Test, Fehlerkorrektur znd Selbstreparatur mit Time-Shared TMR T2 - Tagungsband Dresdner Arbeitstagung für Schaltungs- und Systementwurf (DASS), April 2013 Y1 - 2013 SN - 978-3-8396-0545-5 PB - Fraunhofer-Verl. CY - Stuttgart ER - TY - CHAP A1 - Koal, Tobias A1 - Ulbricht, Markus A1 - Vierhaus, Heinrich Theodor T1 - Virtual TMR Schemes Combining Fault Tolerance and Self Repair T2 - 16th IEEE International Euromicro Conference on Digital System Design, DSD 2013, 4-6 Sep 2013, Santander, Spain Y1 - 2013 SN - 978-0-7695-5074-9 SP - 235 EP - 242 PB - IEEE ER - TY - CHAP A1 - Koal, Tobias A1 - Ulbricht, Markus A1 - Vierhaus, Heinrich Theodor ED - Raik, Jaan T1 - Combining On-Line Fault Detection and Logic Self Repair T2 - IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS 2012), Tallin, Estonia, 18 - 20 April 2012 Y1 - 2012 SN - 978-1-4673-1185-4 SP - 288 EP - 293 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Koal, Tobias A1 - Ulbricht, Markus A1 - Engelke, Piet A1 - Vierhaus, Heinrich Theodor T1 - Kombinierte On-Line-Fehlerkompensation und Selbstreparatur für Logik-Baugruppen T2 - Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, 25. GI/GMM/ITG-Workshop, 24. bis 26. Februar 2013, Dresden Y1 - 2013 PB - Fraunhofer-Institut CY - Dresden ER -