TY - GEN A1 - Rotta, Randolf A1 - Prescher, Thomas A1 - Traue, Jana A1 - Nolte, Jörg T1 - Data Sharing Mechanisms for Parallel Graph Algorithms on the Intel SCC T2 - MARC Symposium at ONERA'2012, July 19th–20th 2012, Toulouse, Frankreich Y1 - 2012 UR - http://hal.archives-ouvertes.fr/hal-00718993 SN - 978-2-7257-0016-8 N1 - Best Paper Award 2012 SP - 13 EP - 18 ER - TY - GEN A1 - Rotta, Randolf A1 - Prescher, Thomas A1 - Traue, Jana A1 - Nolte, Jörg T1 - In-Memory Communication Mechanisms for Many-Cores – Experiences with the Intel SCC T2 - TACC-Intel Highly Parallel Computing Symposium (TIHPCS), Austin/Texas, 2012 N2 - Many-core processors combine fast on-chip communication with access to large amounts of shared memory. This makes it possible to exploit the benefits of distributed as well as shared memory programming models within single parallel algorithms. While large amounts of data can be shared in the memory and caches, coordinating the activities of hundreds of cores relies on cross core communication mechanisms with ultra low latency for very small messages. In this paper we discuss two communication protocols for the Intel SCC and compare them to the MPI implementation of the SCC. Our micro-benchmark results underline that special purpose protocols for small messages make much finer levels of parallelism possible than general purpose message passing systems. Index Terms—many-core, message passing, shared memory Y1 - 2012 UR - http://www.tacc.utexas.edu/documents/13601/4234acca-2171-4465-aa48-7592d5e577f9 UR - http://www.tacc.utexas.edu/documents/13601/06d702ab-3f48-4942-9b07-2fbd880d4310 UR - http://www.tacc.utexas.edu/ti-hpcs12 ER - TY - CHAP A1 - Traue, Jana A1 - Karnapke, Reinhardt A1 - Nolte, Jörg T1 - From Parallel Systems to Wireless Sensor Networks and Back T2 - Technical Report SEEMOO-TR-2012-03, 11. Fachgespräch Sensornetze der GI/ITG Fachgruppe Kommunikation und Verteilte Systeme, 13.-14. September 2012, Technische Universität Darmstadt Y1 - 2012 UR - http://www.seemoo.tu-darmstadt.de/dl/seemoo/seemoo-tr-2012-03.pdf SP - 29 EP - 32 PB - Technische Universität CY - Darmstadt ER - TY - GEN A1 - Rotta, Randolf A1 - Traue, Jana A1 - Prescher, Thomas A1 - Nolte, Jörg T1 - Interrupt-Driven Cross-Core Invocation Mechanisms on the Intel SCC T2 - Proceedings of the Many-core Applications Research Community (MARC) Symposium at RWTH Aachen University 2012 N2 - On many-core processors, both operating system kernels and bare metal applications need efficient cross-core coordination and communication. Although explicit shared- memory programming and message passing might provide the best performance, they also limit the system’s control over scheduling. In contrast, interrupt-driven cross-core invocations provide universal coordination mechanisms that also enable preemptive operations across cores. This paper surveys cross- core invocation mechanisms and their usability with respect to prevalent coordination scenarios. We integrated some of these mechanisms into a bare-metal environment for the Intel SCC pro- cessor and will discuss implementation aspects of the interrupt- driven invocations. In conclusion, such invocation mechanisms provide an expressive platform for future operating systems kernels and bare-metal applications. KW - many-core KW - remote invocations KW - bare-metal Y1 - 2012 SN - 978-3-00-039545-1 SP - 1 EP - 6 PB - Technische Hochschule CY - Aachen ER - TY - GEN A1 - Traue, Jana A1 - Nolte, Jörg A1 - Engel, Philipp A1 - Karnapke, Reinhardt T1 - Using Emulation Software to Predict the Performance of Algorithms on NVRAM T2 - Proceedings of the 7th International ICST Conference on Simulation Tools and Techniques, SIMUTools '14 N2 - Currently, new storage technologies which unite the latency and byte-addressability of DRAM with the persistence of disks are being developed. This non-volatile memory (NVRAM) may start a software revolution. Traditionally, software was developed for two levels of storage and NVRAM reduces the hierarchy to a single-level store. Current research projects are already exploring the potential of NVRAM, but they face a challenge when they want to evaluate the performance: The new hardware is not yet available. In this paper, we discuss why benchmark results which are gained on existing DRAM are insufficient for a prediction of the performance on NVRAM. Either existing instructions have to be changed or new ones have to be introduced. We further show that the bochs emulator can be used to build systems which resemble NVRAM, to predict the NVRAM's consequences, and it even allows a comparison of algorithms for NVRAM. KW - Emulation KW - non-volatile memory Y1 - 2014 SN - 978-1-63190-007-5 U6 - https://doi.org/10.4108/icst.simutools.2014.254796 SP - 142 EP - 146 PB - ICST CY - Brüssel ER - TY - GEN A1 - Köppen, Marcel A1 - Traue, Jana A1 - Borchert, Christoph A1 - Nolte, Jörg A1 - Spinczyk, Olaf ED - Hawblitzel, Chris ED - Muller, Gilles ED - Spinczyk, Olaf T1 - Cache-Line Transactions: Building Blocks for Persistent Kernel Data Structures Enabled by AspectC++ T2 - PLOS ’19, Proceedings of the 10th Workshop on Programming Languages and Operating Systems Y1 - 2019 SN - 978-1-4503-7017-2 U6 - https://doi.org/10.1145/3365137.3365396 SP - 38 EP - 44 PB - acm, The Association for Computing Machinery CY - New York ER -