TY - GEN A1 - Uhlmann, Max A1 - Rizzi, Tommaso A1 - Wen, Jianan A1 - Pérez-Bosch Quesada, Emilio A1 - Al Beattie, Bakr A1 - Ochs, Karlheinz A1 - Pérez, Eduardo A1 - Ostrovskyy, Philip A1 - Carta, Corrado A1 - Wenger, Christian A1 - Kahmen, Gerhard T1 - LUT-based RRAM model for neural accelerator circuit simulation T2 - Proceedings of the 18th ACM International Symposium on Nanoscale Architectures N2 - Neural hardware accelerators have been proven to be energy-efficient when used to solve tasks which can be mapped into an artificial neural network (ANN) structure. Resistive random-access memories (RRAMs) are currently under investigation together with several different memristive devices as promising technologies to build such accelerators combined together with complementary metal-oxide semiconductor (CMOS)-technologies in integrated circuits (ICs). While many research groups are actively developing sophisticated physical-based representations to better understand the underlying phenomena characterizing these devices, not much work has been dedicated to exploit the trade-off between simulation time and accuracy in the definition of low computational demanding models suitable to be used at many abstraction layers. Indeed, the design of complex mixed-signal systems as a neural hardware accelerators requires frequent interaction between the application- and the circuit-level that can be enabled only with the support of accurate and fast-simulating devices’ models. In this work, we propose a solution to fill the aforementioned gap with a lookup table (LUT)-based Verilog-A model of IHP’s 1-transistor-1-RRAM (1T1R) cell. In addition, the implementation challenges of conveying the communication between the abstract ANN simulation and the circuital analysis are tackled with a design flow for resistive neural hardware accelerators that features a custom Python wrapper. As a demonstration of the proposed design flow and 1T1R model, an ANN for the MNIST handwritten digit recognition task is assessed with the last layer verified in circuit simulation. The obtained recognition confidence intervals show a considerable discrepancy between the purely application-level PyTorch simulation and the proposed design flow which spans across the abstraction layers down to the circuital analysis. KW - RRAM KW - Neural network Y1 - 2023 U6 - https://doi.org/10.1145/3611315.3633273 SP - 1 EP - 6 PB - ACM CY - New York, NY, USA ER - TY - GEN A1 - Perez-Bosch Quesada, Emilio A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Rizzi, Tommaso A1 - Wen, Jianan A1 - Ulbricht, Markus A1 - Krstic, Milos A1 - Wenger, Christian A1 - Pérez, Eduardo T1 - Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing T2 - IEEE Transactions on Electron Devices N2 - Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of 8x8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices’ nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems. KW - RRAM KW - Vector Matrix Multiplication KW - variability Y1 - 2023 U6 - https://doi.org/10.1109/TED.2023.3244509 SN - 0018-9383 VL - 70 IS - 4 SP - 2009 EP - 2014 ER - TY - GEN A1 - Perez-Bosch Quesada, Emilio A1 - Rizzi, Tommaso A1 - Gupta, Aditya A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Schubert, Andreas A1 - Pechmann, Stefan A1 - Jia, Ruolan A1 - Uhlmann, Max A1 - Hagelauer, Amelie A1 - Wenger, Christian A1 - Pérez, Eduardo T1 - Multi-Level Programming on Radiation-Hard 1T1R Memristive Devices for In-Memory Computing T2 - 14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023 N2 - This work presents a quasi-static electrical characterization of 1-transistor-1-resistor memristive structures designed following hardness-by-design techniques integrated in the CMOS fabrication process to assure multi-level capabilities in harsh radiation environments. Modulating the gate voltage of the enclosed layout transistor connected in series with the memristive device, it was possible to achieve excellent switching capabilities from a single high resistance state to a total of eight different low resistance states (more than 3 bits). Thus, the fabricated devices are suitable for their integration in larger in-memory computing systems and in multi-level memory applications. Index Terms—radiation-hard, hardness-by-design, memristive devices, Enclosed Layout Transistor, in-memory computing KW - RRAM Y1 - 2023 SN - 979-8-3503-0240-0 U6 - https://doi.org/10.1109/CDE58627.2023.10339525 PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Uhlmann, Max A1 - Rizzi, Tommaso A1 - Wen, Jianan A1 - Quesada, Emilio Pérez-Bosch A1 - Beattie, Bakr Al A1 - Ochs, Karlheinz A1 - Pérez, Eduardo A1 - Ostrovskyy, Philip A1 - Carta, Corrado A1 - Wenger, Christian A1 - Kahmen, Gerhard T1 - End-to-end design flow for resistive neural accelerators T2 - IEEE transactions on computer-aided design of integrated circuits and systems N2 - Neural hardware accelerators have demonstrated notable energy efficiency in tackling tasks, which can be adapted to artificial neural network (ANN) structures. Research is currently directed towards leveraging resistive random-access memories (RRAMs) among various memristive devices. In conjunction with complementary metal-oxide semiconductor (CMOS) technologies within integrated circuits (ICs), RRAM devices are used to build such neural accelerators. In this study, we present a neural accelerator hardware design and verification flow, which uses a lookup table (LUT)-based Verilog-A model of IHP’s one-transistor-one-RRAM (1T1R) cell. In particular, we address the challenges of interfacing between abstract ANN simulations and circuit analysis by including a tailored Python wrapper into the design process for resistive neural hardware accelerators. To demonstrate our concept, the efficacy of the proposed design flow, we evaluate an ANN for the MNIST handwritten digit recognition task, as well as for the CIFAR-10 image recognition task, with the last layer verified through circuit simulation. Additionally, we implement different versions of a 1T1R model, based on quasi-static measurement data, providing insights on the effect of conductance level spacing and device-to-device variability. The circuit simulations tackle both schematic and physical layout assessment. The resulting recognition accuracies exhibit significant differences between the purely application-level PyTorch simulation and our proposed design flow, highlighting the relevance of circuit-level validation for the design of neural hardware accelerators. KW - RRAM Y1 - 2025 U6 - https://doi.org/10.1109/TCAD.2025.3597237 SN - 0278-0070 SN - 1937-4151 SP - 1 EP - 5 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York ER -