TY - GEN A1 - Pechmann, Stefan A1 - Mai, Timo A1 - Völkel, Matthias A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Pérez, Eduardo A1 - Perez-Bosch Quesada, Emilio A1 - Reichenbach, Marc A1 - Wenger, Christian A1 - Hagelauer, Amelie T1 - A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells T2 - Electronics N2 - In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9. KW - RRAM KW - Multilevel switching KW - Programming circuit Y1 - 2021 U6 - https://doi.org/10.3390/electronics10050530 SN - 2079-9292 VL - 10 IS - 5 ER - TY - GEN A1 - Pechmann, Stefan A1 - Mai, Timo A1 - Potschka, Julian A1 - Reiser, Daniel A1 - Reichel, Peter A1 - Breiling, Marco A1 - Reichenbach, Marc A1 - Hagelauer, Amelie T1 - A Low-Power RRAM Memory Block for Embedded, Multi-Level Weight and Bias Storage in Artificial Neural Networks T2 - Micromachines Y1 - 2021 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:bvb:29-opus4-174878 SN - 2072-666X VL - 12 IS - 11 ER -