TY - CHAP A1 - Pashmineh, Sara A1 - Killat, Dirk A1 - Bramburger, Stefan A1 - Hongcheng, Xu A1 - Ortmanns, M. T1 - An LDO using stacked transistors on 65 nm CMOS T2 - 21st European Conference on Circuit Theory and Design (ECCTD), Dresden, September 2013 Y1 - 2013 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Pashmineh, Sara A1 - Killat, Dirk A1 - Bramburger, Stefan T1 - Design of a high-voltage rail-to-rail error amplifier based on standard CMOS used in an LDO T2 - 2016 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE, 15-18 May 2016 N2 - This paper presents the design of a high-voltage (HV) rail-to-rail error amplifier. This circuit controls the output signal of a low drop-out voltage regulator (LDO) according to the reference voltages and based on stacked standard transistors. The circuit is designed using 65 nm CMOS process technology with a nominal voltage of 2.5 V and is optimized for arbitrary values of supply voltage up to 5.0 V. The error amplifier consists of 3 stages and 2 feedback loops. The stages are internally connected rail-to-rail to achieve high GBW and DC accuracy. The simulation and measurement results for the designed HV-error amplifier show that the output signal of the LDO tracks the reference voltages. The circuit design is technology-independent and compatible with scaled CMOS. Y1 - 2016 UR - http://ieeexplore.ieee.org/document/7726693/ SN - 978-1-4673-8721-7 SN - 978-1-4673-8722-4 U6 - https://doi.org/10.1109/CCECE.2016.7726693 SP - 1 EP - 5 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Bramburger, Stefan A1 - Pitonak, Pavol A1 - Killat, Dirk T1 - A unary coded current steering DAC with sequential stepping of the thermometer coded register in 1 and 2 LSB steps T2 - 41st International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO), 21-25 May 2018, Opatija, Croatia N2 - This paper presents an 8-bit current steering DAC that uses unary current sources and a thermometer coded register. The thermometer coded register is controlled by sequentially stepping one or two steps up or down dependent on the control input. The enhanced step size mitigates the slew-rate limitation if the DAC is used in a delta-encoded tracking ADC. The sequential switching of thermometer coded DAC register does not require a binary to thermometer decoder and reduces complexity of error compensation. Y1 - 2018 SN - 978-953-233-095-3 U6 - https://doi.org/10.23919/MIPRO.2018.8400017 SP - 89 EP - 92 PB - IEEE CY - Piscataway ER - TY - GEN A1 - Bramburger, Stefan A1 - Zinke, Benny A1 - Killat, Dirk T1 - Interpolation algorithm for asynchronous ADC-data T2 - Advances in radio science N2 - This paper presents a modified interpolation algo- rithm for signals with variable data rate from asynchronous ADCs. The Adaptive weights Conjugate gradient Toeplitz matrix (ACT) algorithm is extended to operate with a contin- uous data stream. An additional preprocessing of data with constant and linear sections and a weighted overlap of step- by-step into spectral domain transformed signals improve the reconstruction of the asycnhronous ADC signal. The interpo- lation method can be used if asynchronous ADC data is fed into synchronous digital signal processing. Y1 - 2017 UR - https://www.adv-radio-sci.net/15/163/2017/ars-15-163-2017.pdf U6 - https://doi.org/10.5194/ars-15-163-2017 SN - 1684-9973 VL - 15 SP - 163 EP - 168 ER - TY - GEN A1 - Bramburger, Stefan A1 - Killat, Dirk T1 - 10-bit tracking ADC with a multi-bit quantizer, variable step size and segmented current-steering DAC T2 - Advances in Radio Science N2 - This paper presents a 10-bit tracking ADC using a multi-bit quantiser and a segmented current-steering DAC. The quantiser allows a dynamical adjustment of the step size dependent on the input signal waveform. This mitigates the limited slew rate of delta encoded ADCs. Energy consumption induced by 1 LSB ripple is removed by the quantiser. The segmented current-steering DAC allows simple control, good monotonicity and improved transient response when compared to previous design as well as potential power reduction. Y1 - 2019 UR - https://ars.copernicus.org/articles/17/161/2019/ U6 - https://doi.org/10.5194/ars-17-161-2019 SN - 1684-9973 SN - 1684-9965 VL - Vol. 17 SP - 161 EP - 167 ER -