TY - CHAP A1 - Schrape, Oliver A1 - Grass, Eckhard A1 - Petri, Markus A1 - Zeidler, Steffen A1 - Jagdhold, Ulrich A1 - Winkler, Frank T1 - An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis Y1 - 2010 ER - TY - GEN A1 - Winkler, Frank A1 - Kell, Gerald A1 - Schrape, Oliver A1 - Gustat, Hans A1 - Jagdhold, Ulrich T1 - HDL-Synthese und Simulation von Hochgeschwindigkeits-Digitalschaltungen mit gemischten CMOS- und ECL-Bibliotheken Y1 - 2009 ER - TY - CHAP A1 - Schrape, Oliver A1 - Krstic, Milos A1 - Philipp, Gunnar A1 - Winkler, Frank T1 - A Digital Design Flow for Differential ECL High Speed Applications Y1 - 2011 ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Babic, Milan A1 - Li, Yuanqing A1 - Schrape, Oliver A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Use of Decoupling Cells for Mitigation of SET Effects in CMOS Combinational Gates T2 - 25th IEEE International Conference on Electronics Circuits and Systems (ICECS 2018), Bordeaux, France, 09 - 12 December 2018 Y1 - 2018 SN - 978-1-5386-9562-3 SN - 978-1-5386-9116-8 U6 - https://doi.org/10.1109/ICECS.2018.8617996 SP - 361 EP - 364 PB - IEEE CY - Piscataway, NJ ER -