TY - GEN A1 - Rotta, Randolf A1 - Prescher, Thomas A1 - Traue, Jana A1 - Nolte, Jörg T1 - Data Sharing Mechanisms for Parallel Graph Algorithms on the Intel SCC T2 - MARC Symposium at ONERA'2012, July 19th–20th 2012, Toulouse, Frankreich Y1 - 2012 UR - http://hal.archives-ouvertes.fr/hal-00718993 SN - 978-2-7257-0016-8 N1 - Best Paper Award 2012 SP - 13 EP - 18 ER - TY - GEN A1 - Rotta, Randolf A1 - Prescher, Thomas A1 - Traue, Jana A1 - Nolte, Jörg T1 - In-Memory Communication Mechanisms for Many-Cores – Experiences with the Intel SCC T2 - TACC-Intel Highly Parallel Computing Symposium (TIHPCS), Austin/Texas, 2012 N2 - Many-core processors combine fast on-chip communication with access to large amounts of shared memory. This makes it possible to exploit the benefits of distributed as well as shared memory programming models within single parallel algorithms. While large amounts of data can be shared in the memory and caches, coordinating the activities of hundreds of cores relies on cross core communication mechanisms with ultra low latency for very small messages. In this paper we discuss two communication protocols for the Intel SCC and compare them to the MPI implementation of the SCC. Our micro-benchmark results underline that special purpose protocols for small messages make much finer levels of parallelism possible than general purpose message passing systems. Index Terms—many-core, message passing, shared memory Y1 - 2012 UR - http://www.tacc.utexas.edu/documents/13601/4234acca-2171-4465-aa48-7592d5e577f9 UR - http://www.tacc.utexas.edu/documents/13601/06d702ab-3f48-4942-9b07-2fbd880d4310 UR - http://www.tacc.utexas.edu/ti-hpcs12 ER - TY - GEN A1 - Rotta, Randolf A1 - Traue, Jana A1 - Prescher, Thomas A1 - Nolte, Jörg T1 - Interrupt-Driven Cross-Core Invocation Mechanisms on the Intel SCC T2 - Proceedings of the Many-core Applications Research Community (MARC) Symposium at RWTH Aachen University 2012 N2 - On many-core processors, both operating system kernels and bare metal applications need efficient cross-core coordination and communication. Although explicit shared- memory programming and message passing might provide the best performance, they also limit the system’s control over scheduling. In contrast, interrupt-driven cross-core invocations provide universal coordination mechanisms that also enable preemptive operations across cores. This paper surveys cross- core invocation mechanisms and their usability with respect to prevalent coordination scenarios. We integrated some of these mechanisms into a bare-metal environment for the Intel SCC pro- cessor and will discuss implementation aspects of the interrupt- driven invocations. In conclusion, such invocation mechanisms provide an expressive platform for future operating systems kernels and bare-metal applications. KW - many-core KW - remote invocations KW - bare-metal Y1 - 2012 SN - 978-3-00-039545-1 SP - 1 EP - 6 PB - Technische Hochschule CY - Aachen ER - TY - GEN A1 - Rotta, Randolf A1 - Büchner, Steffen A1 - Nolte, Jörg T1 - Middleware for Many-Cores - Why It Is Needed and What Functionality It Should Provide T2 - 4th USENIX Workshop on Hot Topics in Parallelism (HotPar '12), Berkeley, 2012 N2 - Today's multi-cores and future many-cores are NUMA architectures with complex cache hierarchies and multiple memory channels. Depending on the topologies of these memory networks we find everything from true data sharing with shared caches to distributed memory architectures which just pretend to be physical shared memory systems. In fact, most many-cores are hybrid systems that exhibit the characteristics of both distributed systems and SMPs. In this paper we argue in favor of middleware platforms for many-cores. We will discuss the needed functionality in contrast to common distributed system middleware and present micro benchmarks on several architectures to substantiate our claims. Y1 - 2012 UR - https://www.usenix.org/conference/hotpar12/tech-schedule/poster-session ER -