TY - GEN A1 - Wen, Jianan A1 - Vargas, Fabian Luis A1 - Zhu, Fukun A1 - Reiser, Daniel A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Perez, Eduardo A1 - Reichenbach, Marc A1 - Wenger, Christian A1 - Krstic, Milos T1 - RRAMulator : an efficient FPGA-based emulator for RRAM crossbar with device variability and energy consumption evaluation T2 - Microelectronics Reliability N2 - The in-memory computing (IMC) systems based on emerging technologies have gained significant attention due to their potential to enhance performance and energy efficiency by minimizing data movement between memory and processing unit, which is especially beneficial for data-intensive applications. Designing and evaluating systems utilizing emerging memory technologies, such as resistive RAM (RRAM), poses considerable challenges due to the limited support from electronics design automation (EDA) tools for rapid development and design space exploration. Additionally, incorporating technology-dependent variability into system-level simulations is critical to accurately assess the impact on system reliability and performance. To bridge this gap, we propose RRAMulator, a field-programmable gate array (FPGA) based hardware emulator for RRAM crossbar array. To avoid the complex device models capturing the nonlinear current–voltage (IV) relationships that degrade emulation speed and increase hardware utilization, we propose a device and variability modeling approach based on device measurements. We deploy look-up tables (LUTs) for device modeling and use the multivariate kernel density estimation (KDE) method to augment existing data, extending data variety and avoiding repetitive data usage. The proposed emulator achieves cycle-accurate, real-time emulations and provides information such as latency and energy consumption for matrix mapping and vector–matrix multiplications (VMMs). Experimental results show a significant reduction in emulation time compared to conventional behavioral simulations. Additionally, an RRAM-based discrete Fourier transform (DFT) accelerator is analyzed as a case study featuring a range of in-depth system assessments. KW - RRAM Y1 - 2025 U6 - https://doi.org/10.1016/j.microrel.2025.115630 SN - 0026-2714 VL - 168 SP - 1 EP - 10 PB - Elsevier BV CY - Amsterdam ER - TY - GEN A1 - Fritscher, Markus A1 - Uhlmann, Max A1 - Ostrovskyy, Philip A1 - Reiser, Daniel A1 - Chen, Junchao A1 - Wen, Jianan A1 - Schulze, Carsten A1 - Kahmen, Gerhard A1 - Fey, Dietmar A1 - Reichenbach, Marc A1 - Krstic, Milos A1 - Wenger, Christian ED - Wenger, Christian T1 - RISC-V CPU design using RRAM-CMOS standard cells T2 - IEEE transactions on very large scale integration (VLSI) systems N2 - The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely, creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks, we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors, this enables us to construct a nand standard cell, which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS nand gate. We illustrate achievable area savings with a half-adder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates. KW - RRAM KW - Logic gates Y1 - 2025 UR - https://ieeexplore.ieee.org/document/10960690 U6 - https://doi.org/10.1109/TVLSI.2025.3554476 SN - 1063-8210 SP - 1 EP - 9 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York ER - TY - GEN A1 - Doe, Nina A1 - Scharoba, Stefan A1 - Reichenbach, Marc A1 - Herglotz, Christian T1 - Comparison of bluetooth low energy (BLE), Wi-Fi, serial and 5G in IoMT T2 - Proceedings of the 18th international joint conference on biomedical engineering systems and technologies (BIOSTEC 2025), Porto, Portugal : Volume 2 N2 - With the inception of Industry 4.0, incorporating technologies like the Internet of Things (IoT) into healthcare has become essential. This integration is commonly referred to as the Internet of Medical Things (IoMT). The IoMT is the connection of medical devices using wired or wireless data transmission technology to allow data exchange with the goal of improving the overall healthcare delivery. Despite the numerous advantages that IoMT brings into the healthcare process, there are potential performance challenges that may occur if factors such as data quality and reliability of the IoT devices in different environmental settings are not properly considered. The purpose of this paper is to analyse the performance of connected medical IoT devices that are used for heartrate monitoring based on the aforementioned factors. The setup of the IoMT consists of sensor nodes, which transmit the Electrocardiogram (ECG) data through a multi-protocol gateway to a central server for further data processing. This paper presents the performance analysis of the comparison of four communication technologies: Serial (UART), Bluetooth Low Energy (BLE), Wi-Fi, and 5G NR for real-time ECG monitoring applications, while taking notice of environmental factors that may affect performance. The sensor data transmission is evaluated based on round trip time (RTT) latency, ensuring a desirable throughput and minimal or no data loss. The data readings were taken at varying distances (0.1m to 17m) and sampling rates (300Hz and 1000Hz). The experimental results show that while Serial communication achieves the lowest latency (3.96ms - 4.37ms), Wi-Fi demonstrates consistent Gateway-Server performance (40ms - 60msRTT), 5G excels in short-range communication (1.8ms - 2.0ms Sensor Node-Gateway RTT), and BLE providesbalanced performance (4.86ms - 7.57ms latency). Wi-Fi performed better in long-range scenarios (43.48ms -66.23ms RTT) and maintaining stable performance at longer ranges while 5G shows superior performance in short-range, high-frequency scenarios. KW - Internet of Medical Things (IoMT), Performance Evaluation, Wireless Communication, Electrocardiogram (ECG) Monitoring, Real-Time Systems Y1 - 2025 SN - 978-989-758-731-3; ISSN: 2184-4305 U6 - https://doi.org/10.5220/0013321500003911 VL - 2: HEALTHINF SP - 859 EP - 866 PB - Scitepress - Science And Technology Publications Lda. CY - Setúbal, Portugal ER - TY - GEN A1 - Muñoz-Hernandez, Hector Gerardo A1 - Ali, Muhammad A1 - Shahin, Keyvan A1 - Siyavashi, Alireza A1 - Göhringer, Diana A1 - Reichenbach, Marc A1 - Herglotz, Christian A1 - Hübner, Michael T1 - Towards complete open-source environments : FPGA-based GPU overlay controlled by RISC-V T2 - Architecture of computing systems : 38th International Conference, ARCS 2025 Kiel, Germany, April 22–24, 2025, proceedings N2 - Image and signal processing applications have been widely implemented in Field Programmable Gate Arrays (FPGAs) and Graphical Processing Units (GPUs) due to their energy efficiency and performance, respectively. GPUs provide high data processing parallelism and are usually chosen to accelerate applications where low energy consumption is not a high priority. On the other hand, FPGAs are more tailored to hardware solutions due to their reconfigurability, but they struggle to outperform GPUs in data throughput. Soft IP cores implemented on reconfigurable hardware, are an alternative offering advantages from both worlds. Some of these soft-core solutions offer an entire environment that includes scripts to automate their implementation, custom compilers, and other diverse tools. Unfortunately, some of these soft-cores are dependent on proprietary Intellectual Property (IP) or require hardware expertise to use properly. In this work, we propose an extended version of a popular open-source soft GPU, which can now run alongside a soft RISC-V core, and with High-Bandwidth memory (HBM2) compatibility. Previously, this soft GPU was only ready to be deployed in boards with a hard ARM core, but now it can be easily used in FPGAs without this requirement. We also provide an evaluation of how the soft GPU performs with respect to the pure RISC-V core, and a hard ARM core achieving geometric mean speed-ups of 114.60x and 19.72x respectively when performing some image and signal processing applications. Finally, we demonstrate how our soft GPU benefits from the HBM integration. KW - FPGA KW - Soft-core GPU KW - System-On-Chip KW - RISC-V KW - HBM Y1 - 2025 SN - 978-3-032-03280-5 U6 - https://doi.org/https://doi.org/10.1007/978-3-032-03281-2_7 SN - 0302-9743 SP - 94 EP - 108 PB - Springer CY - Berlin ER - TY - GEN A1 - Herglotz, Christian A1 - Jabłoński, Ireneusz A1 - Karnapke, Reinhardt A1 - Shahin, Keyvan A1 - Reichenbach, Marc T1 - Designing intelligent sensor networks : a comprehensive survey of sensing, edge AI, and 5G+/6G connectivity T2 - IEEE access N2 - With the advent of advanced transmission technologies, powerful neural-network architectures, and the availability of cheap sensing solutions, new paradigms for monitoring, controlling, and optimizing any automated system are appearing. While traditionally, sensors simply provided visual or acoustic feedback to human operators of such systems, nowadays, autonomous systems more and more rely on the automatic sensing and processing of such data to react and adapt their control mechanisms. In such complex control systems, sensor networks play a vital role. In this paper, we assess the state of the art in the three main components used within sensor networks: smart sensing elements, transmission technologies, and processing technologies. Concerning the latter, more and more artificial intelligence-based methods are developed and applied turning smart sensor networks into intelligent or even cognitive sensor networks. For the development of such sensing systems, a high variety of performance metrics could be important to the designer. This paper discusses the vast design space for intelligent sensor networks and provides guidance and directions on how to construct future intelligent sensor networks efficiently. KW - 5G, Sensor networks, Edge computing, Energy efficiency, KPIs, Design space, AI Y1 - 2025 U6 - https://doi.org/10.1109/ACCESS.2025.3615205 SN - 2169-3536 VL - 13 SP - 172306 EP - 172325 PB - IEEE CY - Piscataway, NJ ER -