TY - GEN A1 - Pechmann, Stefan A1 - Mai, Timo A1 - Völkel, Matthias A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Pérez, Eduardo A1 - Perez-Bosch Quesada, Emilio A1 - Reichenbach, Marc A1 - Wenger, Christian A1 - Hagelauer, Amelie T1 - A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells T2 - Electronics N2 - In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9. KW - RRAM KW - Multilevel switching KW - Programming circuit Y1 - 2021 U6 - https://doi.org/10.3390/electronics10050530 SN - 2079-9292 VL - 10 IS - 5 ER - TY - GEN A1 - Pechmann, Stefan A1 - Mai, Timo A1 - Potschka, Julian A1 - Reiser, Daniel A1 - Reichel, Peter A1 - Breiling, Marco A1 - Reichenbach, Marc A1 - Hagelauer, Amelie T1 - A Low-Power RRAM Memory Block for Embedded, Multi-Level Weight and Bias Storage in Artificial Neural Networks T2 - Micromachines Y1 - 2021 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:bvb:29-opus4-174878 SN - 2072-666X VL - 12 IS - 11 ER - TY - GEN A1 - Suawa Fogou, Priscile A1 - Meisel, Tenia A1 - Jongmanns, Marcel A1 - Hübner, Michael A1 - Reichenbach, Marc T1 - Modeling and Fault Detection of Brushless Direct Current Motor by Deep Learning Sensor Data Fusion T2 - Sensors Y1 - 2022 U6 - https://doi.org/10.3390/s22093516 SN - 1424-8220 VL - 22 IS - 9 ER - TY - GEN A1 - Fritscher, Markus A1 - Knödtel, Johannes A1 - Mallah, Maen A1 - Pechmann, Stefan A1 - Perez-Bosch Quesada, Emilio A1 - Rizzi, Tommaso A1 - Wenger, Christian A1 - Reichenbach, Marc T1 - Mitigating the Effects of RRAM Process Variation on the Accuracy of Artifical Neural Networks T2 - Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2021. Lecture Notes in Computer Science N2 - Weight storage is a key challenge in the efficient implementation of artificial neural networks. Novel memory technologies such as RRAM are able to greatly improve density and introduce non-volatility and multibit capabilities to this component of ANN accelerators. The usage of RRAM in this domain comes with downsides, mainly caused by cycle-to-cycle and device-to-device variability leading to erroneous readouts, greatly affecting digital systems. ANNs have the ability to compensate for this by their inherent redundancy and usually exhibit a gradual deterioration in the accuracy of the task at hand. This means, that slight error rates can be acceptable for weight storage in an ANN accelerator. In this work we link device-to-device variability to the accuracy of an ANN for such an accelerator. From this study, we can estimate how strongly a certain net is affected by a certain device parameter variability. This methodology is then used to present three mitigation strategies and to evaluate how they affect the reaction of the network to variability: a) Dropout Layers b) Fault-Aware Training c) Redundancy. These mitigations are then evaluated by their ability to improve accuracy and to lower hardware overhead by providing data for a real-word example. We improved this network’s resilience in such a way that it could tolerate double the variation in one of the device parameters (standard deviation of the oxide thickness can be 0.4 nm instead of 0.2 nm while maintaining sufficient accuracy.) KW - RRAM KW - memristive device KW - neural network Y1 - 2022 SN - 978-3-031-04579-0 SN - 978-3-031-04580-6 U6 - https://doi.org/10.1007/978-3-031-04580-6_27 SN - 0302-9743 SN - 1611-3349 SP - 401 EP - 417 PB - Springer ER - TY - GEN A1 - Hernandez, Hector Gerardo Muñoz A1 - Fricke, Florian A1 - Al Kadi, Muhammed A1 - Reichenbach, Marc A1 - Hübner, Michael T1 - Edge GPU based on an FPGA Overlay Architecture using PYNQ T2 - 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI). 2022 Y1 - 2022 SN - 978-1-6654-8128-1 SN - 978-1-6654-8129-8 U6 - https://doi.org/10.1109/SBCCI55532.2022.9893229 ER - TY - GEN A1 - Suawa Fogou, Priscile A1 - Halbinger, Anja A1 - Jongmanns, Marcel A1 - Reichenbach, Marc T1 - Noise-Robust Machine Learning Models for Predictive Maintenance Applications T2 - IEEE Sensors Journal N2 - Predictive maintenance of equipment requires a set of data collected through sensors, from which models will learn behaviors that will allow the automatic detection or prediction of these behaviors. The objective is to anticipate unexpected situations such as sudden equipment stoppages. Industries are noisy environments due to production lines that involve a series of components. As a result, the data will always be obstructed by noise. Noise-robust predictive maintenance models, which include ensemble and deep learning models with and without data fusion, are proposed to enhance the monitoring of industrial equipment. The work reported in this article is based on two components, a milling tool, and a motor, with sound, vibration, and ultrasound data collected in real experiments. Four main tasks were performed, namely the construction of the datasets, the training of the monitoring models without adding artificial noise to the data, the evaluation of the robustness of the previously trained models by injecting several levels of noise into the test data, and the optimization of the models by a proposed noisy training approach. The results show that the models maintain their performances at over 95% accuracy despite adding noise in the test phase. These performances decrease by only 2% at a considerable noise level of 15-dB signal-to-noise ratio (SNR). The noisy training method proved to be an optimal solution for improving the noise robustness and accuracy of convolutional deep learning models, whose performance regression of 2% went from a noise level of 28 to 15 dB like the other models. KW - Accelerometer Y1 - 2023 UR - https://ieeexplore.ieee.org/document/10122864 U6 - https://doi.org/10.1109/JSEN.2023.3273458 SN - 1558-1748 SN - 1530-437X VL - 23 IS - 13 SP - 15081 EP - 15092 ER - TY - GEN A1 - Assafo, Maryam A1 - Lautsch, Martin A1 - Suawa, Priscile Fogou A1 - Jongmanns, Marcel A1 - Hübner, Michael A1 - Reichenbach, Marc A1 - Brockmann, Carsten A1 - Reinhardt, Denis A1 - Langendörfer, Peter T1 - The ForTune Toolbox: Building Solutions for Condition-Based and Predictive Maintenance Focusing on Retrofitting Y1 - 2023 SN - 978-3-8007-6204-0 SN - 978-3-8007-6203-3 N1 - Poster, Tagungsband MikroSystemTechnik Kongress 2023, Dresden, 23. - 25. Oktober 2023 SP - S. 541 PB - VDE Verlag CY - Berlin ER - TY - GEN A1 - Fricke, Florian A1 - Scharoba, Stefan A1 - Rachuj, Sebastian A1 - Konopik, Andreas A1 - Kluge, Florian A1 - Hofstetter, Georg A1 - Reichenbach, Marc ED - Orailoglu, Alex ED - Reichenbach, Marc ED - Jung, Matthias T1 - Application Runtime Estimation for AURIX Embedded MCU Using Deep Learning  T2 - Embedded computer systems : architectures, modeling, and simulation : 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, proceedings Y1 - 2022 SN - 978-3-031-15073-9 SN - 978-3-031-15074-6 U6 - https://doi.org/10.1007/978-3-031-15074-6_15 SP - 235 EP - 249 PB - Springer CY - Cham ER - TY - GEN A1 - Mahmood, Safdar A1 - Scharoba, Stefan A1 - Schorlemer, Jonas A1 - Schulz, Christian A1 - Hübner, Michael A1 - Reichenbach, Marc T1 - Detecting Improvised Land-mines using Deep Neural Networks on GPR Image Dataset targeting FPGAs  T2 - IEEE Nordic Circuits and Systems Conference (NORCAS), 25-26 October 2022, Oslo, Norway Y1 - 2022 SN - 979-8-3503-4550-6 SN - 979-8-3503-4551-3 U6 - https://doi.org/10.1109/norcas57515.2022.9934735 SP - 1 EP - 7 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Mahmood, Safdar A1 - Hübner, Michael A1 - Reichenbach, Marc ED - Palumbo, Francesca ED - Keramidas, Georgios ED - Voros, Nikolaos ED - Diniz, Pedro C. T1 - A Design-Space Exploration Framework for Application-Specific Machine Learning Targeting Reconfigurable Computing T2 - Applied Reconfigurable Computing. Architectures, Tools, and Applications, 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023 Y1 - 2023 SN - 978-3-031-42921-7 SN - 978-3-031-42920-0 U6 - https://doi.org/10.1007/978-3-031-42921-7_27 SP - 371 EP - 374 PB - Springer CY - Cham ER - TY - CHAP A1 - Wen, Jianan A1 - Vargas, Fabian Luis A1 - Zhu, Fukun A1 - Reiser, Daniel A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Pérez, Eduardo A1 - Reichenbach, Marc A1 - Wenger, Christian A1 - Krstic, Milos T1 - Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment T2 - 2024 IEEE 25th Latin American Test Symposium (LATS) N2 - Emerging device technologies such as resistive RAM (RRAM) are increasingly recognized in enhancing system performance, particularly in applications demanding extensive vector-matrix multiplications (VMMs) with high parallelism. However, a significant limitation in current electronics design automation (EDA) tools is their lack of support for rapid prototyping, design space exploration, and the integration of inherent process-dependent device variability into system-level simulations, which is essential for assessing system reliability. To address this gap, we introduce a field-programmable gate array (FPGA) based emulation approach for RRAM crossbars featuring cycle-accurate emulations in real time without relying on complex device models. Our approach is based on pre-generated look-up tables (LUTs) to accurately represent the RRAM device behavior. To efficiently model the device variability at the system level, we propose using the multivariate kernel density estimation (KDE) method to augment the measured RRAM data. The proposed emulator allows precise latency determination for matrix mapping and computation operations. Meanwhile, by coupling with the NeuroSim framework, the corresponding energy consumption can be estimated. In addition to facilitating a range of in-depth system assessments, experimental results suggest a remarkable reduction of emulation time compared to the classic behavioral simulation. KW - RRAM Y1 - 2024 U6 - https://doi.org/10.1109/LATS62223.2024.10534601 PB - IEEE ER - TY - GEN A1 - Fritscher, Markus A1 - Singh, Simranjeet A1 - Rizzi, Tommaso A1 - Baroni, Andrea A1 - Reiser, Daniel A1 - Mallah, Maen A1 - Hartmann, David A1 - Bende, Ankit A1 - Kempen, Tim A1 - Uhlmann, Max A1 - Kahmen, Gerhard A1 - Fey, Dietmar A1 - Rana, Vikas A1 - Menzel, Stephan A1 - Reichenbach, Marc A1 - Krstic, Milos A1 - Merchant, Farhad A1 - Wenger, Christian T1 - A flexible and fast digital twin for RRAM systems applied for training resilient neural networks T2 - Scientific Reports N2 - Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the “ideal memristor” which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a “push button” modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT). KW - RRAM KW - Neural network KW - digital twin Y1 - 2024 U6 - https://doi.org/10.1038/s41598-024-73439-z SN - 2045-2322 VL - 14 IS - 1 PB - Springer Science and Business Media LLC ER - TY - GEN A1 - Fritscher, Markus A1 - Uhlmann, Max A1 - Ostrovskyy, Philip A1 - Reiser, Daniel A1 - Chen, Junchao A1 - Schubert, Andreas A1 - Schulze, Carsten A1 - Kahmen, Gerhard A1 - Fey, Dietmar A1 - Reichenbach, Marc A1 - Krstic, Milos A1 - Wenger, Christian T1 - Area-efficient digital design using RRAM-CMOS standard cells T2 - 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) N2 - Extending the scalability of digital integrated circuits through novel device concepts is an attractive option. Among these concepts, resistive random access memory (RRAM) devices allow fast and nonvolatile operation. However, building large memristive systems is still challenging since large analog circuits have to be designed and integrated. In this paper, we propose a novel solution - the implementation of digital standard cells by the means of RRAM devices. While this methodology is universal, with applications ranging from few-device-circuits to large macroblocks, we demonstrate it for a 2T2R-cell. The benefits of using RRAM devices are demonstrated by implementing a NAND standard cell merely consuming the area of two transistors. This cell is about 25 % smaller than the equivalent CMOS NAND in the same technology. We use these cells to implement a half adder, beating the area of the equivalent CMOS implementation using more sophisticates gates by 15 %. Lastly, we fully integrate this novel standard cell into a digital standard cell library and perform a synthesis and layout of a RISC-V CPU core. KW - RRAM Y1 - 2024 SN - 979-8-3503-5411-9 SN - 979-8-3503-5412-6 U6 - https://doi.org/10.1109/ISVLSI61997.2024.00026 SN - 2159-3477 VL - 18 SP - 81 EP - 87 PB - IEEE ER - TY - GEN A1 - Vishwakarma, Abhinav A1 - Fritscher, Markus A1 - Hagelauer, Amelie A1 - Reichenbach, Marc T1 - An RRAM-based building block for reprogrammable non-uniform sampling ADCs T2 - Information Technology : it Y1 - 2023 U6 - https://doi.org/10.1515/itit-2023-0021 SN - 2196-7032 VL - 65 IS - 1-2 SP - 39 EP - 51 ER - TY - GEN A1 - Schlipf, Jon A1 - Berkmann, Fritz A1 - Yamamoto, Yuji A1 - Reichenbach, Marc A1 - Veleski, Mitko A1 - Kawaguchi, Yuma A1 - Mörz, Florian A1 - Tomm, Jens W. A1 - Weißhaupt, David A1 - Fischer, Inga Anita T1 - Robust Si/Ge heterostructure metasurfaces as building blocks for wavelength-selective photodetectors T2 - Applied Physics Letters Y1 - 2023 U6 - https://doi.org/10.1063/5.0134458 SN - 1077-3118 VL - 122 IS - 12 ER - TY - GEN A1 - Knödtel, Johannes A1 - Rachuj, Sebastian A1 - Reichenbach, Marc T1 - Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the best? T2 - 25th Euromicro Conference on Digital System Design (DSD), 31 August 2022 - 02 September 2022, Maspalomas, Spain Y1 - 2022 U6 - https://doi.org/10.1109/DSD57027.2022.00041 SP - 247 EP - 253 PB - IEEE ER - TY - GEN A1 - Shahin, Keyvan A1 - Rotta, Randolf A1 - Archila, Oscar A1 - Mykytyn, Pavlo A1 - Nattke, Matthias A1 - Reichenbach, Marc A1 - Nolte, Jörg A1 - Natarov, Roman T1 - A Modular Communication Architecture for Adaptive UAV Swarms T2 - 2023 IEEE International Conference on Omni-layer Intelligent Systems (COINS) N2 - Small Unmanned Aerial Vehicles (UAVs) have vast application potential from industrial logistics and disaster monitoring to smart farming, for example, to create maps with Normalized Difference Vegetation Index (NDVI) cameras and AI-based image classification or the precision spot application of fertilizers. Operating multiple UAVs in parallel, including those with different specializations, enables efficient coverage of large areas. While existing research focused mainly on predefined flight formations for swarms or autonomous missions for single UAVs, the focus of this work is on multiple UAVs with individually adaptable missions. We derive communication system requirements from swarm coordination algorithms and present a respective design. The resulting modular architecture enables future research on autonomous adaptive UAV swarms and their use as flying sensor platforms. Y1 - 2023 SN - 979-8-3503-4647-3 SN - 979-8-3503-4648-0 U6 - https://doi.org/10.1109/COINS57856.2023.10189245 PB - IEEE CY - Berlin ER - TY - GEN A1 - Uhlmann, Max A1 - Pérez-Bosch Quesada, Emilio A1 - Fritscher, Markus A1 - Pérez, Eduardo A1 - Schubert, Markus Andreas A1 - Reichenbach, Marc A1 - Ostrovskyy, Philip A1 - Wenger, Christian A1 - Kahmen, Gerhard T1 - One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing T2 - 21st IEEE Interregional NEWCAS Conference (NEWCAS) N2 - The use of resistive random-access memory (RRAM) for in-memory computing (IMC) architectures has significantly improved the energy-efficiency of artificial neural networks (ANN) over the past years. Current RRAM-technologies are physically limited to a defined unambiguously distinguishable number of stable states and a maximum resistive value and are compatible with present complementary metal-oxide semiconductor (CMOS)-technologies. In this work, we improved the accuracy of current ANN models by using increased weight resolutions of memristive devices, combining two or more in-series RRAM cells, integrated in the back end of line (BEOL) of the CMOS process. Based on system level simulations, 1T2R devices were fabricated in IHP's 130nm SiGe:BiCMOS technology node, demonstrating an increased number of states. We achieved an increase in weight resolution from 3 bit in ITIR cells to 6.5 bit in our 1T2R cell. The experimental data of 1T2R devices gives indications for the performance and energy-efficiency improvement in ITNR arrays for ANN applications. KW - RRAM KW - In-Memory Computing Y1 - 2023 SN - 979-8-3503-0024-6 SN - 979-8-3503-0025-3 U6 - https://doi.org/10.1109/NEWCAS57931.2023.10198073 SN - 2474-9672 SN - 2472-467X PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Schwenger, Lars A1 - Holzinger, Philipp A1 - Fey, Dietmar A1 - Munoz-Hernandez, Hector Gerardo A1 - Reichenbach, Marc ED - Orailoglu, Alex ED - Reichenbach, Marc ED - Jung, Matthias T1 - EasyHBM: Simple and Fast HBM Access for FPGAs Using High-Level-Synthesis T2 - Embedded computer systems : architectures, modeling, and simulation : 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, proceedings Y1 - 2022 SN - 978-3-031-15073-9 SN - 978-3-031-15074-6 SP - 43 EP - 60 PB - Springer CY - Cham ER - TY - GEN A1 - Knödtel, Johannes A1 - Munoz-Hernandez, Hector Gerardo A1 - Lehnert, Alexander A1 - Thieu, Gia Bao A1 - Gesper, Sven A1 - Payá-Vayá, Guillermo A1 - Reichenbach, Marc ED - Palumbo, Francesca ED - Keramidas, Georgios ED - Voros, Nikolaos ED - Diniz, Pedro C. T1 - TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs T2 - Applied Reconfigurable Computing. Architectures, Tools, and Applications, 19th International Symposium, ARC 2023, Cottbus, Germany, September 27–29, 2023, Proceedings Y1 - 2023 SN - 978-3-031-42920-0 SN - 978-3-031-42921-7 U6 - https://doi.org/10.1007/978-3-031-42921-7_21 SP - 307 EP - 321 PB - Springer CY - Cham ER - TY - GEN A1 - Reiser, Daniel A1 - Reichenbach, Marc A1 - Rizzi, Tommaso A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Wenger, Christian A1 - Zambelli, Cristian A1 - Bertozzi, Davide T1 - Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations T2 - 21st IEEE Interregional NEWCAS Conference (NEWCAS), 26-28 June 2023, Edinburgh, United Kingdom N2 - In-memory computing with resistive-switching random access memory (RRAM) crossbar arrays has the potential to overcome the major bottlenecks faced by digital hardware for data-heavy workloads such as deep learning. However, RRAM devices are subject to several non-idealities that result in significant inference accuracy drops compared with software baseline accuracy. A critical one is related to the drift of the conductance states appearing immediately at the end of program and verify algorithms that are mandatory for accurate multi-level conductance operation. The support of drift models in state-of-the-art simulation tools of memristive computationin-memory is currently only in the early stage, since they overlook key device- and array-level parameters affecting drift resilience such as the programming algorithm of RRAM cells, the choice of target conductance states and the weight-toconductance mapping scheme. The goal of this paper is to fully expose these parameters to RRAM crossbar designers as a multi-dimensional optimization space of drift resilience. For this purpose, a simulation framework is developed, which comes with the suitable abstractions to propagate the effects of those RRAM crossbar configuration parameters to their ultimate implications over inference performance stability. KW - RRAM Y1 - 2023 SN - 979-8-3503-0024-6 SN - 979-8-3503-0025-3 U6 - https://doi.org/10.1109/NEWCAS57931.2023 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Sridhar, Vivek A1 - Shahin, Keyvan A1 - Breuß, Michael A1 - Reichenbach, Marc T1 - The Polynomial Connection between Morphological Dilation and Discrete Convolution T2 - arXiv Y1 - 2023 U6 - https://doi.org/10.48550/arXiv.2305.03018 SP - 1 EP - 11 ER - TY - GEN A1 - Wen, Jianan A1 - Vargas, Fabian Luis A1 - Zhu, Fukun A1 - Reiser, Daniel A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Perez, Eduardo A1 - Reichenbach, Marc A1 - Wenger, Christian A1 - Krstic, Milos T1 - RRAMulator : an efficient FPGA-based emulator for RRAM crossbar with device variability and energy consumption evaluation T2 - Microelectronics Reliability N2 - The in-memory computing (IMC) systems based on emerging technologies have gained significant attention due to their potential to enhance performance and energy efficiency by minimizing data movement between memory and processing unit, which is especially beneficial for data-intensive applications. Designing and evaluating systems utilizing emerging memory technologies, such as resistive RAM (RRAM), poses considerable challenges due to the limited support from electronics design automation (EDA) tools for rapid development and design space exploration. Additionally, incorporating technology-dependent variability into system-level simulations is critical to accurately assess the impact on system reliability and performance. To bridge this gap, we propose RRAMulator, a field-programmable gate array (FPGA) based hardware emulator for RRAM crossbar array. To avoid the complex device models capturing the nonlinear current–voltage (IV) relationships that degrade emulation speed and increase hardware utilization, we propose a device and variability modeling approach based on device measurements. We deploy look-up tables (LUTs) for device modeling and use the multivariate kernel density estimation (KDE) method to augment existing data, extending data variety and avoiding repetitive data usage. The proposed emulator achieves cycle-accurate, real-time emulations and provides information such as latency and energy consumption for matrix mapping and vector–matrix multiplications (VMMs). Experimental results show a significant reduction in emulation time compared to conventional behavioral simulations. Additionally, an RRAM-based discrete Fourier transform (DFT) accelerator is analyzed as a case study featuring a range of in-depth system assessments. KW - RRAM Y1 - 2025 U6 - https://doi.org/10.1016/j.microrel.2025.115630 SN - 0026-2714 VL - 168 SP - 1 EP - 10 PB - Elsevier BV CY - Amsterdam ER - TY - GEN A1 - Fritscher, Markus A1 - Uhlmann, Max A1 - Ostrovskyy, Philip A1 - Reiser, Daniel A1 - Chen, Junchao A1 - Wen, Jianan A1 - Schulze, Carsten A1 - Kahmen, Gerhard A1 - Fey, Dietmar A1 - Reichenbach, Marc A1 - Krstic, Milos A1 - Wenger, Christian ED - Wenger, Christian T1 - RISC-V CPU design using RRAM-CMOS standard cells T2 - IEEE transactions on very large scale integration (VLSI) systems N2 - The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely, creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks, we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors, this enables us to construct a nand standard cell, which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS nand gate. We illustrate achievable area savings with a half-adder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates. KW - RRAM KW - Logic gates Y1 - 2025 UR - https://ieeexplore.ieee.org/document/10960690 U6 - https://doi.org/10.1109/TVLSI.2025.3554476 SN - 1063-8210 SP - 1 EP - 9 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York ER - TY - GEN A1 - Doe, Nina A1 - Scharoba, Stefan A1 - Reichenbach, Marc A1 - Herglotz, Christian T1 - Comparison of bluetooth low energy (BLE), Wi-Fi, serial and 5G in IoMT T2 - Proceedings of the 18th international joint conference on biomedical engineering systems and technologies (BIOSTEC 2025), Porto, Portugal : Volume 2 N2 - With the inception of Industry 4.0, incorporating technologies like the Internet of Things (IoT) into healthcare has become essential. This integration is commonly referred to as the Internet of Medical Things (IoMT). The IoMT is the connection of medical devices using wired or wireless data transmission technology to allow data exchange with the goal of improving the overall healthcare delivery. Despite the numerous advantages that IoMT brings into the healthcare process, there are potential performance challenges that may occur if factors such as data quality and reliability of the IoT devices in different environmental settings are not properly considered. The purpose of this paper is to analyse the performance of connected medical IoT devices that are used for heartrate monitoring based on the aforementioned factors. The setup of the IoMT consists of sensor nodes, which transmit the Electrocardiogram (ECG) data through a multi-protocol gateway to a central server for further data processing. This paper presents the performance analysis of the comparison of four communication technologies: Serial (UART), Bluetooth Low Energy (BLE), Wi-Fi, and 5G NR for real-time ECG monitoring applications, while taking notice of environmental factors that may affect performance. The sensor data transmission is evaluated based on round trip time (RTT) latency, ensuring a desirable throughput and minimal or no data loss. The data readings were taken at varying distances (0.1m to 17m) and sampling rates (300Hz and 1000Hz). The experimental results show that while Serial communication achieves the lowest latency (3.96ms - 4.37ms), Wi-Fi demonstrates consistent Gateway-Server performance (40ms - 60msRTT), 5G excels in short-range communication (1.8ms - 2.0ms Sensor Node-Gateway RTT), and BLE providesbalanced performance (4.86ms - 7.57ms latency). Wi-Fi performed better in long-range scenarios (43.48ms -66.23ms RTT) and maintaining stable performance at longer ranges while 5G shows superior performance in short-range, high-frequency scenarios. KW - Internet of Medical Things (IoMT), Performance Evaluation, Wireless Communication, Electrocardiogram (ECG) Monitoring, Real-Time Systems Y1 - 2025 SN - 978-989-758-731-3; ISSN: 2184-4305 U6 - https://doi.org/10.5220/0013321500003911 VL - 2: HEALTHINF SP - 859 EP - 866 PB - Scitepress - Science And Technology Publications Lda. CY - Setúbal, Portugal ER - TY - GEN A1 - Muñoz-Hernandez, Hector Gerardo A1 - Ali, Muhammad A1 - Shahin, Keyvan A1 - Siyavashi, Alireza A1 - Göhringer, Diana A1 - Reichenbach, Marc A1 - Herglotz, Christian A1 - Hübner, Michael T1 - Towards complete open-source environments : FPGA-based GPU overlay controlled by RISC-V T2 - Architecture of computing systems : 38th International Conference, ARCS 2025 Kiel, Germany, April 22–24, 2025, proceedings N2 - Image and signal processing applications have been widely implemented in Field Programmable Gate Arrays (FPGAs) and Graphical Processing Units (GPUs) due to their energy efficiency and performance, respectively. GPUs provide high data processing parallelism and are usually chosen to accelerate applications where low energy consumption is not a high priority. On the other hand, FPGAs are more tailored to hardware solutions due to their reconfigurability, but they struggle to outperform GPUs in data throughput. Soft IP cores implemented on reconfigurable hardware, are an alternative offering advantages from both worlds. Some of these soft-core solutions offer an entire environment that includes scripts to automate their implementation, custom compilers, and other diverse tools. Unfortunately, some of these soft-cores are dependent on proprietary Intellectual Property (IP) or require hardware expertise to use properly. In this work, we propose an extended version of a popular open-source soft GPU, which can now run alongside a soft RISC-V core, and with High-Bandwidth memory (HBM2) compatibility. Previously, this soft GPU was only ready to be deployed in boards with a hard ARM core, but now it can be easily used in FPGAs without this requirement. We also provide an evaluation of how the soft GPU performs with respect to the pure RISC-V core, and a hard ARM core achieving geometric mean speed-ups of 114.60x and 19.72x respectively when performing some image and signal processing applications. Finally, we demonstrate how our soft GPU benefits from the HBM integration. KW - FPGA KW - Soft-core GPU KW - System-On-Chip KW - RISC-V KW - HBM Y1 - 2025 SN - 978-3-032-03280-5 U6 - https://doi.org/https://doi.org/10.1007/978-3-032-03281-2_7 SN - 0302-9743 SP - 94 EP - 108 PB - Springer CY - Berlin ER - TY - GEN A1 - Herglotz, Christian A1 - Jabłoński, Ireneusz A1 - Karnapke, Reinhardt A1 - Shahin, Keyvan A1 - Reichenbach, Marc T1 - Designing intelligent sensor networks : a comprehensive survey of sensing, edge AI, and 5G+/6G connectivity T2 - IEEE access N2 - With the advent of advanced transmission technologies, powerful neural-network architectures, and the availability of cheap sensing solutions, new paradigms for monitoring, controlling, and optimizing any automated system are appearing. While traditionally, sensors simply provided visual or acoustic feedback to human operators of such systems, nowadays, autonomous systems more and more rely on the automatic sensing and processing of such data to react and adapt their control mechanisms. In such complex control systems, sensor networks play a vital role. In this paper, we assess the state of the art in the three main components used within sensor networks: smart sensing elements, transmission technologies, and processing technologies. Concerning the latter, more and more artificial intelligence-based methods are developed and applied turning smart sensor networks into intelligent or even cognitive sensor networks. For the development of such sensing systems, a high variety of performance metrics could be important to the designer. This paper discusses the vast design space for intelligent sensor networks and provides guidance and directions on how to construct future intelligent sensor networks efficiently. KW - 5G, Sensor networks, Edge computing, Energy efficiency, KPIs, Design space, AI Y1 - 2025 U6 - https://doi.org/10.1109/ACCESS.2025.3615205 SN - 2169-3536 VL - 13 SP - 172306 EP - 172325 PB - IEEE CY - Piscataway, NJ ER -