TY - GEN A1 - Dorai Swamy Reddy, Keerthi A1 - Pérez, Eduardo A1 - Baroni, Andrea A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Marschmeyer, Steffen A1 - Fraschke, Mirko A1 - Lisker, Marco A1 - Wenger, Christian A1 - Mai, Andreas T1 - Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance T2 - The European Physical Journal B N2 - Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal–insulator–metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2 dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm HfO2 dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology. KW - RRAM Y1 - 2024 U6 - https://doi.org/10.1140/epjb/s10051-024-00821-1 SN - 1434-6028 VL - 97 PB - Springer Science and Business Media LLC ER - TY - GEN A1 - Vinuesa, Guillermo A1 - Garcia, Hector A1 - Duenas, Salvador A1 - Castan, Helena A1 - Iñiguez de la Torre, Ignacio A1 - Gonzalez, Tomas A1 - Dorai Swamy Reddy, Keerthi A1 - Uhlmann, Max A1 - Wenger, Christian A1 - Perez, Eduardo T1 - Effect of the temperature on the performance and dynamic behavior of HfO2-Based Rram Devices T2 - ECS Meeting Abstracts N2 - Over the past decades, the demand for semiconductor memory devices has been steadily increasing, and is currently experiencing an unprecedented boost due to the development and expansion of artificial intelligence. Among emerging high-density non-volatile memories, resistive random-access memory (RRAM) is one of the best recourses for all kind of applications, such as neuromorphic computing or hardware security [1]. Although many materials have been evaluated for RRAM development, some of them with excellent results, HfO2 is one of the established materials in CMOS domain due to its compatibility with standard materials and processes [2]. The main goal of this work is to study the switching capability and stability of HfO2-based RRAMs, as well as to explore their ability in the field of analogue applications, by analyzing the evolution of the resistance states that allow multilevel control. Indeed, analogue operation is a key point for achieving electronic neural synapses in neuromorphic systems, with synaptic weight information encoded in the different resistance states. This research has been carried out over a wide temperature range, between 40 and 340 K, as we are interested in testing the extent to which performance is maintained or modified, with a view to designing neuromorphic circuits that are also suitable in the low-temperature realm. We aim to prove that these simple, fast, high integration density structures can also be used in circuits designed for specific applications, such as aerospace systems. The RRAM devices studied in this work are TiN/Ti/8 nm-HfO2/TiN metal-insulator-metal (MIM) capacitors. Dielectric layers were atomic layer deposited (ALD). It has been demonstrated that the Ti coat in the top electrode acts as a scavenger that absorbs oxygen atoms from the HfO2 layer, and facilitates the creation of conductive filaments of oxygen vacancies [3]. In fact, the oxygen reservoir capability of Ti is well known, as it is able to attract and release oxygen atoms from or to the HfO2 layer during the RRAM operation [4]. The clustering of vacancies extends through the entire thickness of the oxide and, after an electroformig step, it joins the upper and lower electrodes and the device reaches the low resistance state (LRS). By applying adequate electrical signals, the filaments can be partially dissolved, which brings the device into the high-resistance state (HRS), with lower current values. The set process brings the device to the LRS state, while the reset one brings it to the HRS. The dependence of electrical conductivity on external applied electrical excitation allows triggering the device between the both states in a non-volatile manner [5]. The experimental equipment used consisted of a Keithley 4200-SCS semiconductor parameter analyzer and a Lake Shore cryogenic probe station. Fig.1 shows current-voltage cycles measured at different temperatures; the averages values at each temperature, both in logarithmic and linear scale, are also shown. The functional window increases as temperature decreases. The evolutions of set and reset voltage values with temperature are depicted in Fig.2, whereas the current values (measured at 0.1 V) corresponding to the LRS and HRS can be seen in Fig.3. LRS resistance decreases as temperature increases, in agreement with semiconductor behaviour, probably due to a hopping conduction mechanism. Both set and reset voltages decrease as temperature increases; the reset process is smoother at high temperatures. The reduction in reset voltage variability as temperature increases is very notable. Finally, Fig. 4 shows a picture of the transient behaviour; in the right panel of the same figure, the amplitudes of the current transients in the reset state have been included in the external loop. To sum up, the resistive switching phenomena is studied in a wide temperature range. The LRS shows semiconducting behavior with temperature, most likely related to a hopping conduction mechanism. Switching voltages decrease as temperature increases, with a notable reduction in reset voltage variability. An excellent control of intermediate resistance state is shown through current transients at several voltages in the reset process. REFERENCES [1] M. Asif et al., Materials Today Electronics 1, 100004 (2022). [2] S. Slesazeck et al., Nanotechnology 30, 352003 (2019). [3] Z. Fang et al., IEEE Electron Device Letters 35, 9, 912-914 (2014). [4] H. Y. Lee et al., IEEE Electron Device Letters 31, 1, 44-46 (2010). [5] D. J. Wouters et al., Proceedings of the IEEE 103, 8, 1274-1288 (2015). Figure 1 KW - RRAM Y1 - 2024 U6 - https://doi.org/10.1149/MA2024-01211297mtgabs SN - 2151-2043 VL - MA2024-01 IS - 21 SP - 1297 EP - 1297 PB - The Electrochemical Society ER - TY - GEN A1 - Maldonado, David A1 - Baroni, Andrea A1 - Aldana, Samuel A1 - Dorai Swamy Reddy, Keerthi A1 - Pechmann, Stefan A1 - Wenger, Christian A1 - Roldán, Juan Bautista A1 - Pérez, Eduardo T1 - Kinetic Monte Carlo simulation analysis of the conductance drift in Multilevel HfO2-based RRAM devices T2 - Nanoscale N2 - The drift characteristics of valence change memory (VCM) devices have been analyzed through both experimental analysis and 3D kinetic Monte Carlo (kMC) simulations. KW - RRAM Y1 - 2024 U6 - https://doi.org/10.1039/d4nr02975e SN - 2040-3364 VL - 16 IS - 40 SP - 19021 EP - 19033 PB - Royal Society of Chemistry (RSC) ER - TY - GEN A1 - Uhlmann, Max A1 - Krysik, Milosz A1 - Wen, Jianan A1 - Frohberg, Max A1 - Baroni, Andrea A1 - Reddy, Keerthi Dorai Swamy A1 - Pérez, Eduardo A1 - Ostrovskyy, Philip A1 - Piotrowski, Krzysztof A1 - Carta, Corrado A1 - Wenger, Christian A1 - Kahmen, Gerhard T1 - A compact one-transistor-multiple-RRAM characterization platform T2 - IEEE transactions on circuits and systems I : regular papers N2 - Emerging non-volatile memories (eNVMs) such as resistive random-access memory (RRAM) offer an alternative solution compared to standard CMOS technologies for implementation of in-memory computing (IMC) units used in artificial neural network (ANN) applications. Existing measurement equipment for device characterisation and programming of such eNVMs are usually bulky and expensive. In this work, we present a compact size characterization platform for RRAM devices, including a custom programming unit IC that occupies less than 1 mm2 of silicon area. Our platform is capable of testing one-transistor-one-RRAM (1T1R) as well as one-transistor-multiple-RRAM (1TNR) cells. Thus, to the best knowledge of the authors, this is the first demonstration of an integrated programming interface for 1TNR cells. The 1T2R IMC cells were fabricated in the IHP’s 130 nm BiCMOS technology and, in combination with other parts of the platform, are able to provide more synaptic weight resolution for ANN model applications while simultaneously decreasing the energy consumption by 50 %. The platform can generate programming voltage pulses with a 3.3 mV accuracy. Using the incremental step pulse with verify algorithm (ISPVA) we achieve 5 non-overlapping resistive states per 1T1R device. Based on those 1T1R base states we measure 15 resulting state combinations in the 1T2R cells. KW - RRAM KW - Vector Matrix Multiplication Y1 - 2025 U6 - https://doi.org/10.1109/TCSI.2025.3555234 SN - 1549-8328 SP - 1 EP - 12 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York ER -