TY - CHAP A1 - Noack, Andreas A1 - Rotta, Randolf T1 - Multi-level Algorithms for Modularity Clustering N2 - Modularity is a widely used quality measure for graph clusterings. Its exact maximization is prohibitively expensive for large graphs. Popular heuristics progressively merge clusters starting from singletons (coarsening), and optionally improve the resulting clustering by moving vertices between clusters (refinement). This paper experimentally compares existing and new heuristics of this type with respect to their effectiveness (achieved modularity) and runtime. For coarsening, it turns out that the most widely used criterion for merging clusters (modularity increase) is outperformed by other simple criteria, and that a recent multi-step algorithm is no improvement over simple single-step coarsening for these criteria. For refinement, a new multi-level algorithm produces significantly better clusterings than conventional single-level algorithms. A comparison with published benchmark results and algorithm implementations shows that combinations of coarsening and multi-level refinement are competitive with the best algorithms in the literature. KW - Clustering KW - Algorithmen Y1 - 2009 UR - http://www.springerlink.com/content/qugv7708h3806230/ ER - TY - GEN A1 - Prescher, Thomas A1 - Rotta, Randolf A1 - Nolte, Jörg T1 - Flexible Sharing and Replication Mechanisms for Hybrid Memory Architectures T2 - Proceedings of the 4th Many-Core Applications Research Community (MARC) Symposium Y1 - 2011 SN - 978-3-86956-169-1 SP - 67 EP - 72 PB - Univ.-Verl. CY - Potsdam ER - TY - GEN A1 - Rotta, Randolf T1 - On Efficient Message Passing on the Intel SCC T2 - Proceedings, 3rd Many-core Applications Research Community (MARC) Symposium Y1 - 2011 SN - 978-3-86644-717-2 SP - 53 EP - 58 PB - KIT Scientific Publishing CY - Karlsruhe ER - TY - GEN A1 - Rotta, Randolf A1 - Noack, Andreas T1 - Multilevel local search algorithms for modularity clusterin T2 - Journal on Experimental Algorithmics Y1 - 2011 SN - 1084-6654 VL - 16 IS - 2 ER - TY - GEN A1 - Rotta, Randolf A1 - Prescher, Thomas A1 - Traue, Jana A1 - Nolte, Jörg T1 - Data Sharing Mechanisms for Parallel Graph Algorithms on the Intel SCC T2 - MARC Symposium at ONERA'2012, July 19th–20th 2012, Toulouse, Frankreich Y1 - 2012 UR - http://hal.archives-ouvertes.fr/hal-00718993 SN - 978-2-7257-0016-8 N1 - Best Paper Award 2012 SP - 13 EP - 18 ER - TY - GEN A1 - Rotta, Randolf A1 - Büchner, Steffen A1 - Nolte, Jörg T1 - Middleware for Many-Cores - Why It Is Needed and What Functionality It Should Provide T2 - 4th USENIX Workshop on Hot Topics in Parallelism (HotPar '12), Berkeley, 2012 N2 - Today's multi-cores and future many-cores are NUMA architectures with complex cache hierarchies and multiple memory channels. Depending on the topologies of these memory networks we find everything from true data sharing with shared caches to distributed memory architectures which just pretend to be physical shared memory systems. In fact, most many-cores are hybrid systems that exhibit the characteristics of both distributed systems and SMPs. In this paper we argue in favor of middleware platforms for many-cores. We will discuss the needed functionality in contrast to common distributed system middleware and present micro benchmarks on several architectures to substantiate our claims. Y1 - 2012 UR - https://www.usenix.org/conference/hotpar12/tech-schedule/poster-session ER - TY - GEN A1 - Rotta, Randolf A1 - Prescher, Thomas A1 - Traue, Jana A1 - Nolte, Jörg T1 - In-Memory Communication Mechanisms for Many-Cores – Experiences with the Intel SCC T2 - TACC-Intel Highly Parallel Computing Symposium (TIHPCS), Austin/Texas, 2012 N2 - Many-core processors combine fast on-chip communication with access to large amounts of shared memory. This makes it possible to exploit the benefits of distributed as well as shared memory programming models within single parallel algorithms. While large amounts of data can be shared in the memory and caches, coordinating the activities of hundreds of cores relies on cross core communication mechanisms with ultra low latency for very small messages. In this paper we discuss two communication protocols for the Intel SCC and compare them to the MPI implementation of the SCC. Our micro-benchmark results underline that special purpose protocols for small messages make much finer levels of parallelism possible than general purpose message passing systems. Index Terms—many-core, message passing, shared memory Y1 - 2012 UR - http://www.tacc.utexas.edu/documents/13601/4234acca-2171-4465-aa48-7592d5e577f9 UR - http://www.tacc.utexas.edu/documents/13601/06d702ab-3f48-4942-9b07-2fbd880d4310 UR - http://www.tacc.utexas.edu/ti-hpcs12 ER - TY - GEN A1 - Rotta, Randolf A1 - Traue, Jana A1 - Prescher, Thomas A1 - Nolte, Jörg T1 - Interrupt-Driven Cross-Core Invocation Mechanisms on the Intel SCC T2 - Proceedings of the Many-core Applications Research Community (MARC) Symposium at RWTH Aachen University 2012 N2 - On many-core processors, both operating system kernels and bare metal applications need efficient cross-core coordination and communication. Although explicit shared- memory programming and message passing might provide the best performance, they also limit the system’s control over scheduling. In contrast, interrupt-driven cross-core invocations provide universal coordination mechanisms that also enable preemptive operations across cores. This paper surveys cross- core invocation mechanisms and their usability with respect to prevalent coordination scenarios. We integrated some of these mechanisms into a bare-metal environment for the Intel SCC pro- cessor and will discuss implementation aspects of the interrupt- driven invocations. In conclusion, such invocation mechanisms provide an expressive platform for future operating systems kernels and bare-metal applications. KW - many-core KW - remote invocations KW - bare-metal Y1 - 2012 SN - 978-3-00-039545-1 SP - 1 EP - 6 PB - Technische Hochschule CY - Aachen ER - TY - GEN A1 - Nürnberger, Stefan A1 - Rotta, Randolf A1 - Drescher, Gabor A1 - Danner, Daniel A1 - Nolte, Jörg T1 - Diamond Rings: Acknowledged Event Propagation in Many-Core Processors T2 - Euro-Par 2015: Parallel Processing Workshops, Vienna, 2015 N2 - Hardware and software consistency protocols rely on global observability of consistency events. Acknowledged broadcast is an obvious choice to propagate these events. This paper presents a generalized ring topology for parallel event propagation with acknowledged delivery. Implementations for various many-core architectures show increased performance over conventional approaches. Therefore, diamond rings are a prime candidate for implementations of distributed memory models. Y1 - 2015 UR - http://link.springer.com/chapter/10.1007%2F978-3-319-27308-2_58 SN - 978-3-319-27308-2 U6 - https://doi.org/10.1007/978-3-319-27308-2_58 SP - 722 EP - 733 PB - Springer International Publishing CY - Cham ER - TY - GEN A1 - Nürnberger, Stefan A1 - Drescher, Gabor A1 - Rotta, Randolf A1 - Nolte, Jörg A1 - Schröder-Preikschat, Wolfgang T1 - Shared Memory in the Many-Core Age T2 - Euro-Par 2014: Parallel Processing Workshops, Porto, 2014 N2 - With the evolution toward fast networks of many-core processors, the design assumptions at the basis of software-level distributed shared memory (DSM) systems change considerably. But efficient DSMs are needed because they can significantly simplify the implementation of complex distributed algorithms. This paper discusses implications of the many-core evolution and derives a set of reusable elementary operations for future software DSMs. These elementary operations will help in exploring and evaluating new memory models and consistency protocols. Y1 - 2014 UR - http://link.springer.com/chapter/10.1007%2F978-3-319-14313-2_30 SN - 978-3-319-14312-5 U6 - https://doi.org/10.1007/978-3-319-14313-2_30 SP - 351 EP - 362 PB - Springer International Publishing CY - Cham ER - TY - GEN A1 - Rotta, Randolf A1 - Nolte, Jörg A1 - Nikolov, Vladimir A1 - Schubert, Lutz A1 - Bonfert, Stefan A1 - Wesner, Stefan T1 - MyThOS — Scalable OS Design for Extremely Parallel Applications T2 - 2016 Intl IEEE Conferences on Ubiquitous Intelligence Computing, Advanced and Trusted Computing, Scalable Computing and Communications, Cloud and Big Data Computing, Internet of People, and Smart World Congress, 18-21 July 2016 N2 - Many-core architectures trade single-thread performance for a larger number of cores. Scalable throughput can be attained only by a high degree of parallelism, minimized synchronization. Whilst this is achievable for many applications, the operating system still introduces bottlenecks through non-local sharing, synchronization,, message passing. A particular challenge for highly dynamic applications, for example invasive HPC applications, elastic compute clouds, is the management of short-living application threads, processes. This paper discusses OS architecture choices based on microkernel, multikernel, distributed systems designs, our development experience in the context of the MyThOS project. Initial experiments show a much faster thread creation, activation compared to monolithic systems like Linux while providing a more flexible protection, threading model that is better suited for dynamic scenarios. However, despite significant progress in the overall domain of operating systems, the design space for scalable many-core operating systems is yet to be fully explored. Y1 - 2016 SN - 978-1-5090-2771-2 U6 - https://doi.org/10.1109/UIC-ATC-ScalCom-CBDCom-IoP-SmartWorld.2016.0179 SP - 1165 EP - 1172 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Rotta, Randolf A1 - Kuban, Robert A1 - Schöps, Mark Simon A1 - Nolte, Jörg T1 - Dealing with Layers of Obfuscation in pseudo-Uniform Memory Architectures T2 - Euro-Par 2016: Parallel Processing Workshops, Euro-Par 2016 International Workshops, Grenoble, France, August 24-26, 2016 N2 - Pseudo-Uniform Memory Architectures hide the memory's throughput bottlenecks and the network's latency differences in order to provide near-peak average throughput for computations on large datasets. This obviates the need for application-level partitioning and load balancing between NUMA domains but the performance of cross-core communication still depends on the actual placement of the involved variables and cores, which can result in significant variation within applications and between application runs. This paper analyses the pseudo-uniform memory latency on the Intel Xeon Phi Knights Corner processor, derives strategies for the optimised placement of important variables, and discusses the role of localised coordination in pUMA systems. For example, a basic cache line ping-pong benchmark showed a 3x speedup between adjacent cores. Therefore, pUMA systems combined with support for controlled placement of small datasets are an interesting option when processor-wide load balancing is difficult while localised coordination is feasible. Y1 - 2016 SN - 978-3-319-58942-8 SN - 978-3-319-58943-5 U6 - https://doi.org/10.1007/978-3-319-58943-5_55 SP - 685 EP - 696 PB - Springer International Publishing CY - Cham ER - TY - GEN A1 - Kuban, Robert A1 - Rotta, Randolf A1 - Nolte, Jörg ED - Heras, Dora B. ED - Bougé, Luc T1 - Help Your Busy Neighbors: Dynamic Multicasts over Static Topologies T2 - Euro-Par 2017: Parallel Processing Workshops KW - multicast KW - shared memory KW - many-core KW - TLB shootdown Y1 - 2018 SN - 978-3-319-75177-1 SN - 978-3-319-75178-8 U6 - https://doi.org/10.1007/978-3-319-75178-8_51 N1 - viele weitere Herausgeber SP - 636 EP - 657 PB - Springer CY - Cham ER - TY - GEN A1 - Rotta, Randolf A1 - Segabinazzi Ferreira, Raphael A1 - Nolte, Jörg T1 - Real-time dynamic hardware reconfiguration for processors with redundant functional units T2 - Proceedings of the 2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC) N2 - The tiny logic elements in modern integrated circuits increase the rate of transient failures significantly. Therefore, redundancy on various levels is necessary to retain reliability. However, for mixed-criticality scenarios, the typical processor designs offer either too little fault-tolerance or too much redundancy for one part of the applications. Amongst others, we specifically address redundant processor internal functional units (FU) to cope with transient errors and support wear leveling. A real-time operating system (RTOS) was extended to control our prototypical hardware platform and, since it can be configured deterministically within few clock cycles, we are able to reconfigure the FUs dynamically, at process switching time, according to the specified critically of the running processes. Our mechanisms were integrated into the Plasma processor and the Plasma-RTOS. With few changes to the original software code, it was, for example, possible to quickly change from fault-detecting to fault-correcting modes of the processor on demand. KW - Mixed-criticality; Modular redundancy; Reconfiguration; Run-Time Y1 - 2020 SN - 978-1-7281-6958-3 U6 - https://doi.org/10.1109/ISORC49007.2020.00035 SN - 2375-5261 PB - Institute of Electrical and Electronics Engineers Inc. (IEEE) CY - Nashville, TN, USA ER -