TY - GEN A1 - Pérez, Eduardo A1 - Ossorio, Óscar G. A1 - Dueñas, Salvador A1 - Castán, Helena A1 - García, Hector A1 - Wenger, Christian T1 - Programming Pulse Width Assessment for Reliable and Low-Energy Endurance Performance in Al:HfO2-Based RRAM Arrays T2 - Electronics (MDPI) N2 - A crucial step in order to achieve fast and low-energy switching operations in resistive random access memory (RRAM) memories is the reduction of the programming pulse width. In this study, the incremental step pulse with verify algorithm (ISPVA) was implemented by using different pulse widths between 10 μ s and 50 ns and assessed on Al-doped HfO 2 4 kbit RRAM memory arrays. The switching stability was assessed by means of an endurance test of 1k cycles. Both conductive levels and voltages needed for switching showed a remarkable good behavior along 1k reset/set cycles regardless the programming pulse width implemented. Nevertheless, the distributions of voltages as well as the amount of energy required to carry out the switching operations were definitely affected by the value of the pulse width. In addition, the data retention was evaluated after the endurance analysis by annealing the RRAM devices at 150 °C along 100 h. Just an almost negligible increase on the rate of degradation of about 1 μ A at the end of the 100 h of annealing was reported between those samples programmed by employing a pulse width of 10 μ s and those employing 50 ns. Finally, an endurance performance of 200k cycles without any degradation was achieved on 128 RRAM devices by using programming pulses of 100 ns width KW - RRAM KW - Reliability Y1 - 2020 U6 - https://doi.org/10.3390/electronics9050864 SN - 2079-9292 VL - 9 IS - 5 ER - TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Mistroni, Alberto A1 - Perez, Eduardo A1 - Zambelli, Cristian A1 - Wenger, Christian A1 - Krstic, Milos A1 - Bolzani Pöhls, Leticia Maria T1 - ReDiM : an efficient strategy for read disturb mitigation in RRAM-based accelerators T2 - 2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS) N2 - Resistive RAM (RRAM) has emerged as a promising non-volatile memory technology for implementing energy-efficient hardware accelerators within the in-memory computing (IMC) paradigm. However, due to the immature fabrication process and inherent material instabilities, frequent read operations during computations can induce read disturb effects, leading to unintended resistance drift and potential data corruption. Existing mitigation approaches primarily focus on detecting read disturb effects and triggering memory refresh operations. In this work, we propose an architecture-level solution that mitigates read disturb in RRAM-based accelerators. Our strategy employs crossbar duplication and decomposes the single high input pulse into two lower-amplitude pulses, effectively minimizing the risk of read disturb. To validate our approach, we develop a simulation framework that incorporates measurement data from characterized RRAM devices under read disturb stress conditions. Experimental results on VGG-8 with CIFAR-10 demonstrate that the proposed method significantly mitigates inference accuracy degradation caused by read disturb in RRAM-based accelerators, while incurring modest area and energy overheads of 12.32% and 2.15%, respectively. This work provides a practical and scalable solution for enhancing the robustness of RRAM-based accelerators in edge and high-performance computing applications. KW - RRAM KW - Resistive RAM KW - In-memory Computing KW - AI Accelerator KW - Read Disturb KW - Reliability Y1 - 2025 SN - 979-8-3315-3334-2 U6 - https://doi.org/10.1109/IOLTS65288.2025.11117065 SP - 1 EP - 7 PB - IEEE CY - Piscataway, NJ ER -