TY - GEN A1 - Segabinazzi Ferreira, Raphael A1 - George, Nevin A1 - Chen, Junchao A1 - Hübner, Michael A1 - Krstic, Milos A1 - Nolte, Jörg A1 - Vierhaus, Heinrich Theodor T1 - Configurable Fault Tolerant Circuits and System Level Integration for Self-Awareness T2 - Proceedings of the Work in Progress Session held in connection with SEAA 2019, the 45th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2019, the 22nd EUROMICRO Conference on Digital System Design N2 - Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on- line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system. Y1 - 2019 SN - 978-3-902457-54-7 U6 - https://doi.org/10.26127/BTUOpen-5050 PB - SEA-Publications CY - Kallithea, Chalkidiki (Greece) ER - TY - GEN A1 - Jenihhin, Maksim A1 - Hamdioui, Said A1 - Sonza-Reorda, Matteo A1 - Krstic, Milos A1 - Langendörfer, Peter A1 - Sauer, Christian A1 - Klotz, Anton A1 - Hübner, Michael A1 - Nolte, Jörg A1 - Vierhaus, Heinrich Theodor A1 - Selimis, Georgions A1 - Alexandrescu, Dan A1 - Taouil, Mottaqiallah A1 - Schrijen, Geert-Jan A1 - Sterpone, Luca A1 - Squillero, Giovanni A1 - Dyka, Zoya A1 - Raik, Jaan T1 - RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems T2 - ArXiv.org Y1 - 2019 UR - https://arxiv.org/abs/1912.01561 ER - TY - GEN A1 - Segabinazzi Ferreira, Raphael A1 - Nolte, Jörg A1 - Vargas, Fabian A1 - George, Nevin A1 - Hübner, Michael T1 - Run-time Hardware Reconfiguration of Functional Units to Support Mixed-Critical Applications T2 - IEEE Latin American Test Symposium (LATS), Maceió, Brazil Y1 - 2020 U6 - https://doi.org/10.1109/LATS49555.2020.9093692 ER - TY - GEN A1 - Hasani, Alireza A1 - Lopacinski, Lukasz A1 - Büchner, Steffen A1 - Nolte, Jörg A1 - Kraemer, Rolf T1 - A Modified Shuffling Method to Split the Critical Path Delay in Layered Decoding of QC-LDPC Codes T2 - 30th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC 2019), Istanbul, Turkey, 08 - 11 September 2019 Y1 - 2019 SN - 978-1-5386-8110-7 SN - 978-1-5386-8111-4 U6 - https://doi.org/10.1109/PIMRC.2019.8904435 SN - 2166-9589 SN - 2166-9570 ER - TY - GEN A1 - Hasani, Alireza A1 - Lopacinski, Lukasz A1 - Büchner, Steffen A1 - Nolte, Jörg A1 - Kraemer, Rolf T1 - An Unnoticed Property in QC-LDPC Codes to Find the Message from the Codeword in Non-Systematic Codes T2 - 28th European Conference on Networks and Communications (EuCNC 2019), Valencia, Spain, 18 - 21 June 2019 Y1 - 2019 SN - 978-1-7281-0546-8 SN - 978-1-7281-0545-1 U6 - https://doi.org/10.1109/EuCNC.2019.8801957 SN - 2575-4912 PB - IEEE ER - TY - GEN A1 - Hasani, Alireza A1 - Lopacinski, Lukasz A1 - Büchner, Steffen A1 - Nolte, Jörg A1 - Kraemer, Rolf T1 - A Modified Rejection-Based Architecture to Find the First Two Minima in Min-Sum-Based LDPC Decoders T2 - IEEE Wireless Communications and Networking Conference (WCNC 2020), Seoul, South Korea, 25 - 28 May 2020 Y1 - 2020 SN - 978-1-7281-3106-1 SN - 978-1-7281-3107-8 U6 - https://doi.org/10.1109/WCNC45663.2020.9120630 SN - 1558-2612 PB - IEEE ER - TY - CHAP A1 - Büchner, Steffen A1 - Nolte, Jörg A1 - Hasani, Alireza A1 - Kraemer, Rolf A1 - Lopacinski, Lukasz ED - Kraemer, Rolf ED - Scholz, Stefan T1 - End2End100 - Communication Protocol Processing for Ultra High Data Rates T2 - Wireless 100 Gbps and beyond : architectures, spproaches and findings of German Research Foundation (DFG) priority programme SPP 1655 Y1 - 2020 SN - 978-3-96439-003-5 SP - 359 EP - 396 PB - IHP GmbH CY - Frankfurt (Oder) ET - 1. Auflage ER - TY - GEN A1 - Rotta, Randolf A1 - Segabinazzi Ferreira, Raphael A1 - Nolte, Jörg T1 - Real-time dynamic hardware reconfiguration for processors with redundant functional units T2 - Proceedings of the 2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC) N2 - The tiny logic elements in modern integrated circuits increase the rate of transient failures significantly. Therefore, redundancy on various levels is necessary to retain reliability. However, for mixed-criticality scenarios, the typical processor designs offer either too little fault-tolerance or too much redundancy for one part of the applications. Amongst others, we specifically address redundant processor internal functional units (FU) to cope with transient errors and support wear leveling. A real-time operating system (RTOS) was extended to control our prototypical hardware platform and, since it can be configured deterministically within few clock cycles, we are able to reconfigure the FUs dynamically, at process switching time, according to the specified critically of the running processes. Our mechanisms were integrated into the Plasma processor and the Plasma-RTOS. With few changes to the original software code, it was, for example, possible to quickly change from fault-detecting to fault-correcting modes of the processor on demand. KW - Mixed-criticality; Modular redundancy; Reconfiguration; Run-Time Y1 - 2020 SN - 978-1-7281-6958-3 U6 - https://doi.org/10.1109/ISORC49007.2020.00035 SN - 2375-5261 PB - Institute of Electrical and Electronics Engineers Inc. (IEEE) CY - Nashville, TN, USA ER - TY - GEN A1 - Büchner, Steffen A1 - Hasani, Alireza A1 - Lopacinski, Lukasz A1 - Kraemer, Rolf A1 - Nolte, Jörg T1 - 100 Gbit/s End-to-End Communication: Adding Flexibility with Protocol Templates T2 - 2018 IEEE 43rd Conference on Local Computer Networks (LCN) N2 - High-speed protocol processing that provides data-rates of 100 Gbit/s and beyond to the application stresses the whole communication system up to its outer limits. Such a system can only be utilized by employing highly specialized, application specific protocols, that are tailored for certain communication parameters, such as the packet loss rate. However, the requirements for most applications are not static, and a protocol designer cannot anticipate all possible communication conditions upfront. The contradiction between specialized protocols and unknown communication parameters can be solved by adapting the protocol implementation on demand to the current communication conditions. However, such an approach needs a protocol description language that allows the automatic specialization of protocols. In this paper, we present the Protocol Engine Template Language (PETL), that allows the automatic implementation of protocols by a constructive approach for a variety of communication conditions from protocol implementation templates. KW - Protocol Template KW - 100 Gbit/s end-to-end KW - End2End 100 KW - Soft Real-Time Protocol Stream Processing Y1 - 2018 SN - 978-1-5386-4413-3 SN - 978-1-5386-4414-0 U6 - https://doi.org/10.1109/LCN.2018.8638078 SN - 0742-1303 SP - 263 EP - 266 ET - 1. Auflage ER - TY - GEN A1 - Eichler, Christian A1 - Hofmeier, Henriette A1 - Reif, Stefan A1 - Hönig, Timo A1 - Nolte, Jörg A1 - Schröder-Preikschat, Wolfgang T1 - Neverlast: Towards the Design und Implementation of the NVM-based Everlasting Operating System T2 - Hawaii International Conference on System Sciences 2021 - HICSS-54 KW - operating systems KW - non-volatile memory KW - software development for mobile devices, the internet-of-things, and cyber physical systems energy Y1 - 2021 UR - https://scholarspace.manoa.hawaii.edu/handle/10125/71491 U6 - https://doi.org/10.24251/HICSS.2021.870 SP - 7227 EP - 7236 PB - Scholarspace ER -