TY - GEN A1 - Lohs, Stefan A1 - Siegemund, Gerry A1 - Nolte, Jörg A1 - Turau, Volker T1 - Influence of Topology-Fluctuations on Self-Stabilizing Algorithms T2 - International Conference on Distributed Computing in Sensor Systems (DCOSS) N2 - Self-stabilizing systems have in theory the unique and provable ability, to always return to a valid system state even in the face of failures. These properties are certainly desirable for domains like wireless ad-hoc networks with numerous unpredictable faults. Unfortunately, the time in which the system returns to a valid state is not predictable and potentially unbound. The failure rate typically depends on physical phenomena and in self-stabilizing systems each node tries to react to failures in an inherently adaptive fashion by the cyclic observation of the states of its neighbors. When state changes are either too quick or too slow the system might never reach a state that is sufficiently stable for a specific task. In this paper, we investigate the influences of the error rate on the (stability) convergence time on the basis of topology information acquired in real network experiments. This allows us to asses the asymptotic behavior of relevant self-stabilizing algorithms in typical wireless networks. KW - wireless sensor networks KW - network topology KW - topology KW - stability analysis KW - wireless networks KW - Ad hoc networks Y1 - 2016 SN - 978-1-5090-1460-6 SN - 978-1-5090-1461-3 SP - 122 EP - 124 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Büchner, Steffen A1 - Lopacinski, Lukasz A1 - Nolte, Jörg A1 - Kraemer, Rolf T1 - 100 Gbit/s End-to-End Communication: Designing Scalable Protocols with Soft Real-Time Stream Processing T2 - 2016 IEEE 41st Conference on Local Computer Networks, 7-10 Nov. 2016 Y1 - 2016 UR - http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7796771&isnumber=7796740 SN - 978-1-5090-2054-6 U6 - https://doi.org/10.1109/LCN.2016.25 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Rotta, Randolf A1 - Nolte, Jörg A1 - Nikolov, Vladimir A1 - Schubert, Lutz A1 - Bonfert, Stefan A1 - Wesner, Stefan T1 - MyThOS — Scalable OS Design for Extremely Parallel Applications T2 - 2016 Intl IEEE Conferences on Ubiquitous Intelligence Computing, Advanced and Trusted Computing, Scalable Computing and Communications, Cloud and Big Data Computing, Internet of People, and Smart World Congress, 18-21 July 2016 N2 - Many-core architectures trade single-thread performance for a larger number of cores. Scalable throughput can be attained only by a high degree of parallelism, minimized synchronization. Whilst this is achievable for many applications, the operating system still introduces bottlenecks through non-local sharing, synchronization,, message passing. A particular challenge for highly dynamic applications, for example invasive HPC applications, elastic compute clouds, is the management of short-living application threads, processes. This paper discusses OS architecture choices based on microkernel, multikernel, distributed systems designs, our development experience in the context of the MyThOS project. Initial experiments show a much faster thread creation, activation compared to monolithic systems like Linux while providing a more flexible protection, threading model that is better suited for dynamic scenarios. However, despite significant progress in the overall domain of operating systems, the design space for scalable many-core operating systems is yet to be fully explored. Y1 - 2016 SN - 978-1-5090-2771-2 U6 - https://doi.org/10.1109/UIC-ATC-ScalCom-CBDCom-IoP-SmartWorld.2016.0179 SP - 1165 EP - 1172 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Rotta, Randolf A1 - Kuban, Robert A1 - Schöps, Mark Simon A1 - Nolte, Jörg T1 - Dealing with Layers of Obfuscation in pseudo-Uniform Memory Architectures T2 - Euro-Par 2016: Parallel Processing Workshops, Euro-Par 2016 International Workshops, Grenoble, France, August 24-26, 2016 N2 - Pseudo-Uniform Memory Architectures hide the memory's throughput bottlenecks and the network's latency differences in order to provide near-peak average throughput for computations on large datasets. This obviates the need for application-level partitioning and load balancing between NUMA domains but the performance of cross-core communication still depends on the actual placement of the involved variables and cores, which can result in significant variation within applications and between application runs. This paper analyses the pseudo-uniform memory latency on the Intel Xeon Phi Knights Corner processor, derives strategies for the optimised placement of important variables, and discusses the role of localised coordination in pUMA systems. For example, a basic cache line ping-pong benchmark showed a 3x speedup between adjacent cores. Therefore, pUMA systems combined with support for controlled placement of small datasets are an interesting option when processor-wide load balancing is difficult while localised coordination is feasible. Y1 - 2016 SN - 978-3-319-58942-8 SN - 978-3-319-58943-5 U6 - https://doi.org/10.1007/978-3-319-58943-5_55 SP - 685 EP - 696 PB - Springer International Publishing CY - Cham ER - TY - GEN A1 - Lopacinski, Lukasz A1 - Brzozowski, Marcin A1 - Kraemer, Rolf A1 - Büchner, Steffen A1 - Nolte, Jörg T1 - Improving Energy Efficiency using a Link Adaptation Algorithm Dedicated for 100 Gbps Wireless Communication T2 - AEÜ - International Journal of Electronics and Communications Y1 - 2017 SN - 1434-8411 SN - 1618-0399 VL - 81 SP - 67 EP - 73 ER - TY - CHAP A1 - Lopacinski, Lukasz A1 - Brzozowski, Marcin A1 - Kraemer, Rolf A1 - KrishneGowda, Karthik A1 - Büchner, Steffen A1 - Nolte, Jörg T1 - Towards 100 Gbps Wireless Communication: Investigation of FEC Interleavers for PSSS-15 Spreading T2 - IEEE EUROCON 2017, 17th International Conference on Smart Technologies, Ohrid, Macedonia, 6-8 July 2017 Y1 - 2017 SN - 978-1-5090-3843-5 SP - 619 EP - 623 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Büchner, Steffen A1 - Lopacinski, Lukasz A1 - Kraemer, Rolf A1 - Nolte, Jörg T1 - Protocol Processing for 100 Gbit/s and Beyond - A Soft Real-Time Approach in Hardware and Software T2 - Frequenz: Journal of RF-Engineering and Telecommunications Y1 - 2017 SN - 2191-6349 SN - 0016-1136 VL - 71 IS - 9-10 SP - 427 EP - 438 ER - TY - GEN A1 - Büchner, Steffen A1 - Nolte, Jörg A1 - Hasani, Alireza A1 - Kraemer, Rolf T1 - 100 Gbit/s End-to-End Communication: Low Overhead On-Demand Protocol Replacement in High Data Rate Communication Systems T2 - 42nd Conference on Local Computer Networks (LCN), 9-12 Oct. 2017, Singapore KW - Protocol Replacement KW - 100 Gbit/s end-to-end KW - End2End100 KW - Soft Real-Time Protocol Stream Processing Y1 - 2017 UR - http://ieeexplore.ieee.org/document/8109360/ SN - 978-1-5090-6523-3 U6 - https://doi.org/10.1109/LCN.2017.40 SP - 231 EP - 234 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Karnapke, Reinhardt A1 - Nolte, Jörg T1 - Unidirectional Link Counter - a Routing Protocol for Wireless Sensor Networks with Many Unidirectional Links T2 - 14th Annual Mediterranean Ad Hoc Networking Workshop (Med-Hoc-Net 2015), Vilamoura, Portugal, 17 - 18 June 2015 Y1 - 2015 SN - 978-1-4673-7306-7 SP - 1 EP - 7 PB - IEEE CY - Piscataway ER - TY - GEN A1 - Kuban, Robert A1 - Rotta, Randolf A1 - Nolte, Jörg ED - Heras, Dora B. ED - Bougé, Luc T1 - Help Your Busy Neighbors: Dynamic Multicasts over Static Topologies T2 - Euro-Par 2017: Parallel Processing Workshops KW - multicast KW - shared memory KW - many-core KW - TLB shootdown Y1 - 2018 SN - 978-3-319-75177-1 SN - 978-3-319-75178-8 U6 - https://doi.org/10.1007/978-3-319-75178-8_51 N1 - viele weitere Herausgeber SP - 636 EP - 657 PB - Springer CY - Cham ER - TY - GEN A1 - Segabinazzi Ferreira, Raphael A1 - Nolte, Jörg T1 - Low latency reconfiguration mechanism for fine-grained processor internal functional units T2 - 2019 IEEE Latin American Test Symposium (LATS) N2 - The strive for performance, low power consumption, and less chip area have been diminishing the reliability and the time to fault occurrences due to wear out of electronic devices. Recent research has shown that functional units within processors usually execute a different amount of operations when running programs. Therefore, these units present different individual wear out during their lifetime. Most existent schemes for reconfiguration of processors due to fault detection and other processor parameters are done at the level of cores which is a costly way to achieve redundancy. This paper presents a low latency (approximately 1 clock cycle) software controlled mechanism to reconfigure units within processor cores according to predefined parameters. Such reconfiguration capability delivers features like wear out balance of processor functional units, configuration of units according to the criticality of tasks running on an operating system and configurations to gain in performance (e.g. parallel execution) when possible. The focus of this paper is to show the implemented low latency reconfiguration mechanism and highlight its possible main features. Y1 - 2019 SN - 978-1-7281-1756-0 U6 - https://doi.org/10.1109/LATW.2019.8704560 SN - 2373-0862 ER - TY - GEN A1 - Segabinazzi Ferreira, Raphael A1 - George, Nevin A1 - Chen, Junchao A1 - Hübner, Michael A1 - Krstic, Milos A1 - Nolte, Jörg A1 - Vierhaus, Heinrich Theodor T1 - Configurable Fault Tolerant Circuits and System Level Integration for Self-Awareness T2 - Proceedings of the Work in Progress Session held in connection with SEAA 2019, the 45th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2019, the 22nd EUROMICRO Conference on Digital System Design N2 - Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on- line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system. Y1 - 2019 SN - 978-3-902457-54-7 U6 - https://doi.org/10.26127/BTUOpen-5050 PB - SEA-Publications CY - Kallithea, Chalkidiki (Greece) ER - TY - GEN A1 - Jenihhin, Maksim A1 - Hamdioui, Said A1 - Sonza-Reorda, Matteo A1 - Krstic, Milos A1 - Langendörfer, Peter A1 - Sauer, Christian A1 - Klotz, Anton A1 - Hübner, Michael A1 - Nolte, Jörg A1 - Vierhaus, Heinrich Theodor A1 - Selimis, Georgions A1 - Alexandrescu, Dan A1 - Taouil, Mottaqiallah A1 - Schrijen, Geert-Jan A1 - Sterpone, Luca A1 - Squillero, Giovanni A1 - Dyka, Zoya A1 - Raik, Jaan T1 - RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems T2 - ArXiv.org Y1 - 2019 UR - https://arxiv.org/abs/1912.01561 ER - TY - GEN A1 - Segabinazzi Ferreira, Raphael A1 - Nolte, Jörg A1 - Vargas, Fabian A1 - George, Nevin A1 - Hübner, Michael T1 - Run-time Hardware Reconfiguration of Functional Units to Support Mixed-Critical Applications T2 - IEEE Latin American Test Symposium (LATS), Maceió, Brazil Y1 - 2020 U6 - https://doi.org/10.1109/LATS49555.2020.9093692 ER - TY - GEN A1 - Hasani, Alireza A1 - Lopacinski, Lukasz A1 - Büchner, Steffen A1 - Nolte, Jörg A1 - Kraemer, Rolf T1 - A Modified Shuffling Method to Split the Critical Path Delay in Layered Decoding of QC-LDPC Codes T2 - 30th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC 2019), Istanbul, Turkey, 08 - 11 September 2019 Y1 - 2019 SN - 978-1-5386-8110-7 SN - 978-1-5386-8111-4 U6 - https://doi.org/10.1109/PIMRC.2019.8904435 SN - 2166-9589 SN - 2166-9570 ER - TY - GEN A1 - Hasani, Alireza A1 - Lopacinski, Lukasz A1 - Büchner, Steffen A1 - Nolte, Jörg A1 - Kraemer, Rolf T1 - An Unnoticed Property in QC-LDPC Codes to Find the Message from the Codeword in Non-Systematic Codes T2 - 28th European Conference on Networks and Communications (EuCNC 2019), Valencia, Spain, 18 - 21 June 2019 Y1 - 2019 SN - 978-1-7281-0546-8 SN - 978-1-7281-0545-1 U6 - https://doi.org/10.1109/EuCNC.2019.8801957 SN - 2575-4912 PB - IEEE ER - TY - GEN A1 - Hasani, Alireza A1 - Lopacinski, Lukasz A1 - Büchner, Steffen A1 - Nolte, Jörg A1 - Kraemer, Rolf T1 - A Modified Rejection-Based Architecture to Find the First Two Minima in Min-Sum-Based LDPC Decoders T2 - IEEE Wireless Communications and Networking Conference (WCNC 2020), Seoul, South Korea, 25 - 28 May 2020 Y1 - 2020 SN - 978-1-7281-3106-1 SN - 978-1-7281-3107-8 U6 - https://doi.org/10.1109/WCNC45663.2020.9120630 SN - 1558-2612 PB - IEEE ER - TY - CHAP A1 - Büchner, Steffen A1 - Nolte, Jörg A1 - Hasani, Alireza A1 - Kraemer, Rolf A1 - Lopacinski, Lukasz ED - Kraemer, Rolf ED - Scholz, Stefan T1 - End2End100 - Communication Protocol Processing for Ultra High Data Rates T2 - Wireless 100 Gbps and beyond : architectures, spproaches and findings of German Research Foundation (DFG) priority programme SPP 1655 Y1 - 2020 SN - 978-3-96439-003-5 SP - 359 EP - 396 PB - IHP GmbH CY - Frankfurt (Oder) ET - 1. Auflage ER - TY - GEN A1 - Rotta, Randolf A1 - Segabinazzi Ferreira, Raphael A1 - Nolte, Jörg T1 - Real-time dynamic hardware reconfiguration for processors with redundant functional units T2 - Proceedings of the 2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC) N2 - The tiny logic elements in modern integrated circuits increase the rate of transient failures significantly. Therefore, redundancy on various levels is necessary to retain reliability. However, for mixed-criticality scenarios, the typical processor designs offer either too little fault-tolerance or too much redundancy for one part of the applications. Amongst others, we specifically address redundant processor internal functional units (FU) to cope with transient errors and support wear leveling. A real-time operating system (RTOS) was extended to control our prototypical hardware platform and, since it can be configured deterministically within few clock cycles, we are able to reconfigure the FUs dynamically, at process switching time, according to the specified critically of the running processes. Our mechanisms were integrated into the Plasma processor and the Plasma-RTOS. With few changes to the original software code, it was, for example, possible to quickly change from fault-detecting to fault-correcting modes of the processor on demand. KW - Mixed-criticality; Modular redundancy; Reconfiguration; Run-Time Y1 - 2020 SN - 978-1-7281-6958-3 U6 - https://doi.org/10.1109/ISORC49007.2020.00035 SN - 2375-5261 PB - Institute of Electrical and Electronics Engineers Inc. (IEEE) CY - Nashville, TN, USA ER - TY - GEN A1 - Büchner, Steffen A1 - Hasani, Alireza A1 - Lopacinski, Lukasz A1 - Kraemer, Rolf A1 - Nolte, Jörg T1 - 100 Gbit/s End-to-End Communication: Adding Flexibility with Protocol Templates T2 - 2018 IEEE 43rd Conference on Local Computer Networks (LCN) N2 - High-speed protocol processing that provides data-rates of 100 Gbit/s and beyond to the application stresses the whole communication system up to its outer limits. Such a system can only be utilized by employing highly specialized, application specific protocols, that are tailored for certain communication parameters, such as the packet loss rate. However, the requirements for most applications are not static, and a protocol designer cannot anticipate all possible communication conditions upfront. The contradiction between specialized protocols and unknown communication parameters can be solved by adapting the protocol implementation on demand to the current communication conditions. However, such an approach needs a protocol description language that allows the automatic specialization of protocols. In this paper, we present the Protocol Engine Template Language (PETL), that allows the automatic implementation of protocols by a constructive approach for a variety of communication conditions from protocol implementation templates. KW - Protocol Template KW - 100 Gbit/s end-to-end KW - End2End 100 KW - Soft Real-Time Protocol Stream Processing Y1 - 2018 SN - 978-1-5386-4413-3 SN - 978-1-5386-4414-0 U6 - https://doi.org/10.1109/LCN.2018.8638078 SN - 0742-1303 SP - 263 EP - 266 ET - 1. Auflage ER - TY - GEN A1 - Eichler, Christian A1 - Hofmeier, Henriette A1 - Reif, Stefan A1 - Hönig, Timo A1 - Nolte, Jörg A1 - Schröder-Preikschat, Wolfgang T1 - Neverlast: Towards the Design und Implementation of the NVM-based Everlasting Operating System T2 - Hawaii International Conference on System Sciences 2021 - HICSS-54 KW - operating systems KW - non-volatile memory KW - software development for mobile devices, the internet-of-things, and cyber physical systems energy Y1 - 2021 UR - https://scholarspace.manoa.hawaii.edu/handle/10125/71491 U6 - https://doi.org/10.24251/HICSS.2021.870 SP - 7227 EP - 7236 PB - Scholarspace ER - TY - GEN A1 - Köhler, Sven A1 - Herzog, Benedict A1 - Hönig, Timo A1 - Wenzel, Lukas A1 - Plauth, Max A1 - Nolte, Jörg A1 - Polze, Andreas A1 - Schröder-Preikschat, Wolfgang T1 - Pinpoint the Joules: Unifying Runtime-Support for Energy Measurements on Heterogeneous Systems T2 - 2020 IEEE/ACM International Workshop on Runtime and Operating Systems for Supercomputers (ROSS) N2 - For the design and operation of today's computer systems, power and energy requirements are highest priorities. Unlike performance analyses, however, power and energy measurements of heterogeneous systems are difficult to conduct. Especially at the system-software level, performing power and energy measurements remains challenging. Yet, such measurements are essential to improve software components for low power and high energy-efficiency.In this paper, we analyze and discuss the power and energy characteristics of several heterogeneous systems with up to 20 cores (160 hardware threads) and 1 TB of main memory. For the analyzed systems, we outline challenges regarding power and energy measurements and show ways to overcome limitations (i.e., sampling constraints). To improve the current state of the art in power and energy measurements at the system-software level, we present the design and implementation of PINPOINT, an energy-profiling tool which unifies different power and energy measurement interfaces. Y1 - 2020 UR - https://www.computer.org/csdl/proceedings-article/ross/2020/104600a031/1pXlZMpoXTO VL - 1 SP - 31 EP - 40 PB - IEEE Xplore ER - TY - GEN A1 - Giersch, Oliver A1 - Nolte, Jörg T1 - Fast and Portable Concurrent FIFO Queues with Deterministic Memory Reclamation T2 - IEEE Transactions on Parallel and Distributed Systems (TPDS) KW - memory management KW - instruction sets KW - hazards KW - indexes KW - runtime KW - arrays KW - synchronization Y1 - 2021 U6 - https://doi.org/10.1109/TPDS.2021.3097901 SN - 1045-9219 SN - 1558-2183 VL - 33 IS - 3 SP - 604 EP - 616 ER -