TY - GEN A1 - Fricke, Florian A1 - Mahmood, Safdar A1 - Hoffmann, Javier Eduardo A1 - Ali, Muhammad A1 - Shahin, Keyvan A1 - Hübner, Michael A1 - Göhringer, Diana T1 - Domain Adaptive Processor Architectures T2 - Kommunikation und Bildverarbeitung in der Automation Y1 - 2020 SN - 978-3-662-59895-5 SN - 978-3-662-59894-8 U6 - https://doi.org/10.1007/978-3-662-59895-5_23 SN - 2522-8579 SN - 2522-8587 SP - 315 EP - 330 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Veleski, Mitko A1 - Muñoz-Hernandez, Hector Gerardo A1 - Ali, Muhammad A1 - Le Jeune, Laurens A1 - Goedemé, Toon A1 - Mentens, Nele A1 - Vandendriessche, Jurgen A1 - Lhoest, Lancelot A1 - Da Silva, Bruno A. A1 - Touhafi, Abdellah A1 - Goehringer, Diana A1 - Hübner, Michael T1 - Embedded AI Techniques for Industrial Applications T2 - 31st International Conference on Field-Programmable Logic and Applications (FPL), Dresden, Germany, 30 August-3 September 2021 Y1 - 2021 SN - 978-1-6654-3759-2 U6 - https://doi.org/10.1109/FPL53798.2021.00071 SP - 374 EP - 375 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Brandalero, Marcelo A1 - Ali, Muhammad A1 - Le Jeune, Laurens A1 - Munoz-Hernandez, Hector Gerardo A1 - Veleski, Mitko A1 - Silva, Bruno da A1 - Lemeire, Jan A1 - Van Beeck, Kristof A1 - Touhafi, Abdellah A1 - Goedemé, Toon A1 - Mentens, Nele A1 - Göhringer, Diana A1 - Hübner, Michael T1 - AITIA: Embedded AI Techniques for Industrial Applications T2 - International Conference on Omni-Layer Intelligent Systems (COINS), 31 August-2 September 2020, Barcelona, Spain Y1 - 2020 SN - 978-1-7281-6371-0 U6 - https://doi.org/10.1109/COINS49042.2020.9191672 SP - 1 EP - 7 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Muñoz-Hernandez, Hector Gerardo A1 - Ali, Muhammad A1 - Shahin, Keyvan A1 - Siyavashi, Alireza A1 - Göhringer, Diana A1 - Reichenbach, Marc A1 - Herglotz, Christian A1 - Hübner, Michael T1 - Towards complete open-source environments : FPGA-based GPU overlay controlled by RISC-V T2 - Architecture of computing systems : 38th International Conference, ARCS 2025 Kiel, Germany, April 22–24, 2025, proceedings N2 - Image and signal processing applications have been widely implemented in Field Programmable Gate Arrays (FPGAs) and Graphical Processing Units (GPUs) due to their energy efficiency and performance, respectively. GPUs provide high data processing parallelism and are usually chosen to accelerate applications where low energy consumption is not a high priority. On the other hand, FPGAs are more tailored to hardware solutions due to their reconfigurability, but they struggle to outperform GPUs in data throughput. Soft IP cores implemented on reconfigurable hardware, are an alternative offering advantages from both worlds. Some of these soft-core solutions offer an entire environment that includes scripts to automate their implementation, custom compilers, and other diverse tools. Unfortunately, some of these soft-cores are dependent on proprietary Intellectual Property (IP) or require hardware expertise to use properly. In this work, we propose an extended version of a popular open-source soft GPU, which can now run alongside a soft RISC-V core, and with High-Bandwidth memory (HBM2) compatibility. Previously, this soft GPU was only ready to be deployed in boards with a hard ARM core, but now it can be easily used in FPGAs without this requirement. We also provide an evaluation of how the soft GPU performs with respect to the pure RISC-V core, and a hard ARM core achieving geometric mean speed-ups of 114.60x and 19.72x respectively when performing some image and signal processing applications. Finally, we demonstrate how our soft GPU benefits from the HBM integration. KW - FPGA KW - Soft-core GPU KW - System-On-Chip KW - RISC-V KW - HBM Y1 - 2025 SN - 978-3-032-03280-5 U6 - https://doi.org/https://doi.org/10.1007/978-3-032-03281-2_7 SN - 0302-9743 SP - 94 EP - 108 PB - Springer CY - Berlin ER -