TY - CHAP A1 - Lopacinski, Lukasz A1 - Eissa, Mohamed Hussein A1 - Panic, Goran A1 - Brzozowski, Marcin A1 - Hasani, Alireza A1 - Kraemer, Rolf T1 - Implementation of a Multi-Core Data Link Layer Processor for THz Communication T2 - IEEE 87th Vehicular Technology Conference (VTC 2018), 03 - 06 June 2018, Porto, Portugal Y1 - 2018 SN - 978-1-5386-6355-4 U6 - https://doi.org/10.1109/VTCSpring.2018.8417522 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Lopacinski, Lukasz A1 - Marinkovic, Miroslav A1 - Panic, Goran A1 - Eissa, Mohamed Hussein A1 - Hasani, Alireza A1 - Krishnegowda, Karthik A1 - Kraemer, Rolf T1 - Data Link Layer Processor for 100 Gbps Terahertz Wireless Communications in 28 nm CMOS Technology T2 - IEEE Access Y1 - 2019 U6 - https://doi.org/10.1109/ACCESS.2019.2907156 SN - 2169-3536 IS - 7 SP - 44489 EP - 44502 ER - TY - GEN A1 - Lopacinski, Lukasz A1 - Eissa, Mohamed Hussein A1 - Panic, Goran A1 - Hasani, Alireza A1 - Kraemer, Rolf T1 - Modular Data Link Layer Processing for THz Communication T2 - 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2019), Cluj-Napoca, Romania, 24 - 26 April 2019 Y1 - 2019 SN - 978-1-7281-0073-9 SN - 978-1-7281-0072-2 SN - 978-1-7281-0074-6 U6 - https://doi.org/10.1109/DDECS.2019.8724657 SN - 2473-2117 SN - 2334-3133 ER - TY - GEN A1 - Panic, Goran A1 - Eissa, Mohamed Hussein A1 - Lopacinski, Lukasz A1 - Maletic, Nebojsa A1 - Kraemer, Rolf T1 - Modular Baseband Processing for mm-Wave and THz Communication T2 - Proceedings of the 8th Small Systems Simulation Symposium 2020, Niš, Serbia, 12th-14th February 2020 Y1 - 2020 UR - http://ssss.elfak.rs/wp-content/uploads/2020/02/8.pdf SP - 49 EP - 53 ER - TY - GEN A1 - Eissa, Mohamed Hussein A1 - Fischer, Gunter A1 - Mausolf, Thomas A1 - Rücker, Holger A1 - Malignaggi, Andrea A1 - Kahmen, Gerhard T1 - 220-320-GHz J-Band 4-Way Power Amplifier in Advanced 130-nm BiCMOS Technology T2 - IEEE Microwave and Wireless Components Letters Y1 - 2022 U6 - https://doi.org/10.1109/LMWC.2022.3181407 SN - 1531-1309 SN - 1558-1764 VL - 32 IS - 11 SP - 1335 EP - 1338 ER - TY - GEN A1 - Eissa, Mohamed Hussein T1 - A 240-GHz VMPS with 1.2° and 0.35 dB RMS errors in 130 nm BiCMOS:C technology T2 - IEEE Microwave and Wireless Technology Letters (MWTL) N2 - This work presents a low phase error (PE) and amplitude error (AE) vector modulator phase shifter (VMPS) in the J -band. The influence of the IQ crosstalk RF impairment on the performance is analyzed for different vector summation implementations, guiding to the VMPS architecture choice and design optimization. The chosen architecture consists of an IQ analog-controlled voltage-gain amplifier (IQ-VGA), Branchline coupler, and a Wilkinson combiner. Test structures for the variable-gain amplifier (VGA) and the VMPS are manufactured and measured in a 130-nm BiCMOS technology ( fT/fmax = 300/500 GHz). For the phase resolution of 11.25°, the VMPS achieves an average rms PE and AE of 1.2° and 0.35 dB, respectively, with equivalent to 5.5 -bits control voltage across the frequency band 220–260 GHz. The VMPS consumes 60 mW from 2.5-V supply and occupies 0.2 mm2 of silicon area. This work presents the least PE and AE across a wide bandwidth for VMPS in silicon technologies above 200 GHz, which is crucial for large-scale beam-steering arrays. Y1 - 2024 UR - https://ieeexplore.ieee.org/document/10419351 U6 - https://doi.org/10.1109/LMWT.2024.3357203 SN - 2771-957X SN - 2771-9588 VL - 34 IS - 3 SP - 295 EP - 297 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York ER -