TY - PAT A1 - Stamenković, Zoran A1 - Kraemer, Rolf A1 - Krstic, Milos A1 - Tittelbach-Helmrich, Klaus A1 - Ignacio, S. A1 - Javier, V. A1 - Jesus, P. A1 - Jesus, I. T1 - MIMO Transmission in IEEE 802.11 WLAN Systems Y1 - 2009 ER - TY - PAT A1 - Krstic, Milos A1 - Fan, X. A1 - Grass, Eckhard T1 - GALS Circuit Block and GALS Circuit Device Suitable for Bursty Data Transfer Y1 - 2009 ER - TY - PAT A1 - Fan, X. A1 - Grass, Eckhard A1 - Krstic, Milos T1 - Aussetzbarer Taktgenerator Y1 - 2009 ER - TY - PAT A1 - Krstic, Milos A1 - Fan, X. A1 - Grass, Eckhard T1 - GALS Circuit Block and GALS Circuit Device Suitable for Bursty Data Transfer Y1 - 2008 ER - TY - THES A1 - Krstic, Milos T1 - Request-driven GALS technique for datapath architectures KW - Gals KW - System integration KW - Asynchroner Entwurf KW - EMI KW - BIST Y1 - 2006 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-000000888 ER - TY - PAT A1 - Grass, Eckhard A1 - Krstic, Milos T1 - Asynchrone Hüllschaltung für eine global asynchrone, lokale synchrone (GALS) Schaltung Y1 - 2006 ER - TY - RPRT A1 - Tittelbach-Helmrich, Klaus A1 - Krstic, Milos A1 - Fiebig, Norbert A1 - Methfessel, Michael T1 - Test Report for WLAN Access Point Chipset, Deliverable D5.2 Y1 - 2005 ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Ilic, Aleksandar A1 - Stamenković, Zoran A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - An Overview of the Modeling and Simulation of the Single Event Transients at the Circuit Level T2 - 30th International Conference on Microelectronics (MIEL), 9-11 Oct. 2017, Nis, Serbia Y1 - 2017 SN - 978-1-5386-2563-7 SN - 978-1-5386-2561-3 U6 - https://doi.org/10.1109/MIEL.2017.8190065 SP - 35 EP - 44 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - An Analysis of the Operation and SET Robustness of a CMOS Pulse Stretching Circuit T2 - 20thInternational Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2017), 19-21 April 2017 Dresden Y1 - 2017 SN - 978-1-5386-0472-4 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Petrovic, Vladimir A1 - Nenadovic, Miljana A1 - Breitenreiter, Anselm A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Design of an On-Chip System for the SET Pulse Width Measurement T2 - Euromicro Conference on Digital System Design, 30 Aug.-1 Sept., Vienna, Austria 2017 Y1 - 2017 SN - 978-1-5386-2146-2 SP - 111 EP - 118 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Babic, Milan A1 - Li, Yuanqing A1 - Schrape, Oliver A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Use of Decoupling Cells for Mitigation of SET Effects in CMOS Combinational Gates T2 - 25th IEEE International Conference on Electronics Circuits and Systems (ICECS 2018), Bordeaux, France, 09 - 12 December 2018 Y1 - 2018 SN - 978-1-5386-9562-3 SN - 978-1-5386-9116-8 U6 - https://doi.org/10.1109/ICECS.2018.8617996 SP - 361 EP - 364 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Ilic, Aleksandar A1 - Stamenković, Zoran A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - An Overview of the Current Models for the Circuit-level Simulations of Single Event Transients T2 - Book of abstracts, 5th International Conference on Radiation and Applications in Various Fields of Research (RAD 2017), June 12-16, 2017, Budva, Montenegro Y1 - 2017 SP - S. 184 ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Stamenković, Zoran A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Impact of Resistive Open and Bridge Defects on the SET Robustness of CMOS Combinational Logic T2 - IEEE East-West Design & Test Symposium (EWDTS 2018), Kazan, Russia, 14 - 17 September 2018 Y1 - 2018 SN - 978-1-5386-5709-6 U6 - https://doi.org/10.1109/EWDTS.2018.8524748 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Nenadovic, Miljana A1 - Petrovic, Vladimir A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Evaluation of the Pulse Stretcher for Detection of Very Short Single Event Transients T2 - Book of abstracts, 5th International Conference on Radiation and Applications in Various Fields of Research (RAD 2017), Budva, Montenegro, 2017 Y1 - 2017 UR - http://rad2017.rad-conference.org/news.php SP - S. 214 ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Comparison of the SET Sensitivity of Standard Logic Gates Designed in 130 nm CMOS Technology T2 - 30th International Conference on Microelectronics (MIEL), 9-11 Oct. 2017, Nis, Serbia Y1 - 2017 SN - 978-1-5386-2563-7 SN - 978-1-5386-2561-3 U6 - https://doi.org/10.1109/MIEL.2017.8190106 SP - 217 EP - 220 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Assessment of the Amplitude-duration Criterion for SET Robusness Evaluation T2 - 23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Thessaloniki, Greece, 3-5 July 2017 Y1 - 2017 SN - 978-1-5386-0352-9 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Wen, Jianan A1 - Vargas, Fabian Luis A1 - Zhu, Fukun A1 - Reiser, Daniel A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Perez, Eduardo A1 - Reichenbach, Marc A1 - Wenger, Christian A1 - Krstic, Milos T1 - Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment T2 - 2024 IEEE 25th Latin American Test Symposium (LATS) N2 - Emerging device technologies such as resistive RAM (RRAM) are increasingly recognized in enhancing system performance, particularly in applications demanding extensive vector-matrix multiplications (VMMs) with high parallelism. However, a significant limitation in current electronics design automation (EDA) tools is their lack of support for rapid prototyping, design space exploration, and the integration of inherent process-dependent device variability into system-level simulations, which is essential for assessing system reliability. To address this gap, we introduce a field-programmable gate array (FPGA) based emulation approach for RRAM crossbars featuring cycle-accurate emulations in real time without relying on complex device models. Our approach is based on pre-generated look-up tables (LUTs) to accurately represent the RRAM device behavior. To efficiently model the device variability at the system level, we propose using the multivariate kernel density estimation (KDE) method to augment the measured RRAM data. The proposed emulator allows precise latency determination for matrix mapping and computation operations. Meanwhile, by coupling with the NeuroSim framework, the corresponding energy consumption can be estimated. In addition to facilitating a range of in-depth system assessments, experimental results suggest a remarkable reduction of emulation time compared to the classic behavioral simulation. KW - RRAM Y1 - 2024 U6 - https://doi.org/10.1109/LATS62223.2024.10534601 PB - IEEE ER -