TY - CHAP A1 - Troya Chinchilla, Alfonso Luis A1 - Maharatna, Koushik A1 - Krstic, Milos A1 - Grass, Eckhard A1 - Kraemer, Rolf T1 - OFDM Synchronizer Implementation for an IEEE 802.11a Compliant Modem Y1 - 2002 ER - TY - THES A1 - Krstic, Milos T1 - Request-driven GALS technique for datapath architectures KW - Gals KW - System integration KW - Asynchroner Entwurf KW - EMI KW - BIST Y1 - 2006 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-000000888 ER - TY - CHAP A1 - Zeidler, Steffen A1 - Bystrov, Alexander A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - On-line Testing of Bundled-Data Asynchronous Handshake Protocols Y1 - 2010 ER - TY - GEN A1 - Krstic, Milos A1 - Krol, T. A1 - Grass, Eckhard T1 - Reducing EMI using GALS Approach Y1 - 2010 ER - TY - CHAP A1 - Bertozzi, Davide A1 - Strano, A. A1 - Ludovici, D. A1 - Pavlidis, V. A1 - Angiolini, F. A1 - Krstic, Milos T1 - The Synchronization Challenge Y1 - 2010 ER - TY - PAT A1 - Stamenković, Zoran A1 - Kraemer, Rolf A1 - Krstic, Milos A1 - Tittelbach-Helmrich, Klaus A1 - Ignacio, S. A1 - Javier, V. A1 - Jesus, P. A1 - Jesus, I. T1 - MIMO Transmission in IEEE 802.11 WLAN Systems Y1 - 2009 ER - TY - CHAP A1 - Fan, X. A1 - Krstic, Milos A1 - Grass, Eckhard A1 - Wolf, Ch. T1 - A GALS FFT Processor with Clock Modulation for Low-EMI Applications Y1 - 2010 ER - TY - CHAP A1 - Elvira, Victor A1 - Ibáñez, Jesús A1 - Santamaria, I. A1 - Krstic, Milos A1 - Tittelbach-Helmrich, Klaus A1 - Stamenković, Zoran T1 - Baseband Processor for RF-MIMO WLAN Y1 - 2010 ER - TY - CHAP A1 - Stamenković, Zoran A1 - Tittelbach-Helmrich, Klaus A1 - Krstic, Milos A1 - Ibáñez, Jesús A1 - Elvira, Victor A1 - Santamaria, I. T1 - MAC and Baseband Hardware Platforms for RF-MIMO WLAN Y1 - 2010 ER - TY - BOOK A1 - Fan, X. A1 - Krstic, Milos A1 - Grass, Eckhard T1 - Improvements in Pausible Clocking Scheme for High-Throughput and High-Reliability GALS Systems Design Y1 - 2010 PB - Springer ER - TY - CHAP A1 - Miletic, E. A1 - Krstic, Milos A1 - Piz, M. A1 - Methfessel, Michael T1 - Digital Automatic Gain Control Integrated on WLAN Platform Y1 - 2008 ER - TY - CHAP A1 - Krstic, Milos A1 - Piz, M. A1 - Ehrig, Marcus A1 - Grass, Eckhard T1 - OFDM Datapath Baseband Processor for 1 Gbps Datarate Y1 - 2008 ER - TY - JOUR A1 - Troya Chinchilla, Alfonso Luis A1 - Maharatna, Koushik A1 - Krstic, Milos A1 - Grass, Eckhard A1 - Jagdhold, Ulrich A1 - Kraemer, Rolf T1 - Low-Power VLSI Implementation of the Inner Receiver for OFDM-Based WLAN Systems Y1 - 2008 ER - TY - JOUR A1 - Krstic, Milos A1 - Grass, Eckhard A1 - Heer, Ch. T1 - A GALS Approach to Improve System Integration Y1 - 2008 ER - TY - CHAP A1 - Fan, X. A1 - Krstic, Milos A1 - Grass, Eckhard T1 - Analysis and Optimization of Pausible Clocking Based GALS Design Y1 - 2009 ER - TY - CHAP A1 - Krol, T. A1 - Krstic, Milos A1 - Fan, X. A1 - Grass, Eckhard T1 - GALS Systems Applied for EMI Reduction Y1 - 2009 ER - TY - CHAP A1 - Zeidler, Steffen A1 - Ehrig, Marcus A1 - Krstic, Milos A1 - Augustin, Michael A1 - Wolf, Christoph A1 - Kraemer, Rolf T1 - Ultra Low Cost Asynchronous Handshake Checker Y1 - 2009 ER - TY - GEN A1 - Krstic, Milos A1 - Fan, X. A1 - Grass, Eckhard A1 - Gürkaynak, F. T1 - GALS for Bursty Data Transfer Based on the Clock Coupling Y1 - 2009 ER - TY - PAT A1 - Krstic, Milos A1 - Fan, X. A1 - Grass, Eckhard T1 - GALS Circuit Block and GALS Circuit Device Suitable for Bursty Data Transfer Y1 - 2008 ER - TY - PAT A1 - Fan, X. A1 - Krstic, Milos A1 - Grass, Eckhard T1 - Aussetzbarer Taktgenerator Y1 - 2008 ER - TY - PAT A1 - Fan, X. A1 - Grass, Eckhard A1 - Krstic, Milos T1 - Aussetzbarer Taktgenerator Y1 - 2009 ER - TY - PAT A1 - Krstic, Milos A1 - Fan, X. A1 - Grass, Eckhard T1 - GALS Circuit Block and GALS Circuit Device Suitable for Bursty Data Transfer Y1 - 2009 ER - TY - CHAP A1 - Stamenković, Zoran A1 - Tittelbach-Helmrich, Klaus A1 - Krstic, Milos A1 - Perez, J. A1 - Via, J. A1 - Ibáñez, Jesús T1 - Architecture of an Analog Combining MIMO System Compliant to IEEE 802.11a Y1 - 2009 ER - TY - CHAP A1 - Piz, M. A1 - Krstic, Milos A1 - Ehrig, Marcus A1 - Grass, Eckhard T1 - An OFDM Baseband Receiver for Short-Range Communication at 60 GHz Y1 - 2009 ER - TY - JOUR A1 - Troya Chinchilla, Alfonso Luis A1 - Maharatna, Koushik A1 - Krstic, Milos A1 - Grass, Eckhard A1 - Jagdhold, Ulrich A1 - Kraemer, Rolf T1 - Efficient Inner Receiver Design for OFDM-Based WLAN Systems: Algorithm and Architecture Y1 - 2007 ER - TY - JOUR A1 - Krstic, Milos A1 - Grass, Eckhard A1 - Gürkaynak, F. A1 - Vivet, P. T1 - Globally Asynchronous, Locally Synchronous Circuits: Overview & Outlook Y1 - 2007 ER - TY - CHAP A1 - Maharatna, Koushik A1 - Troya Chinchilla, Alfonso Luis A1 - Krstic, Milos A1 - Grass, Eckhard T1 - On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder Y1 - 2006 ER - TY - CHAP A1 - Grass, Eckhard A1 - Herzel, F. A1 - Piz, M. A1 - Schmalz, K. A1 - Sun, Yaoming A1 - Glisic, S. A1 - Krstic, Milos A1 - Tittelbach-Helmrich, Klaus A1 - Ehrig, Marcus A1 - Winkler, W. A1 - Scheytt, J. Christoph A1 - Kraemer, Rolf T1 - 60 GHz SiGe-BiCMOS Radio for OFDM Transmission Y1 - 2007 ER - TY - JOUR A1 - Krstic, Milos A1 - Grass, Eckhard A1 - Stahl, C. A1 - Piz, M. T1 - System Integration by Request-driven GALS Design Y1 - 2006 ER - TY - PAT A1 - Grass, Eckhard A1 - Krstic, Milos T1 - Asynchrone Hüllschaltung für eine global asynchrone, lokale synchrone (GALS) Schaltung Y1 - 2006 ER - TY - PAT A1 - Krstic, Milos A1 - Grass, Eckhard T1 - GALS-Schaltung mit arbitriertem eingangs- und ausgangsseitigem Taktantrieb Y1 - 2007 ER - TY - CHAP A1 - Krstic, Milos A1 - Grass, Eckhard T1 - GALSification of IEEE 802.11a Baseband Processor Y1 - 2004 ER - TY - CHAP A1 - Maharatna, Koushik A1 - Troya Chinchilla, Alfonso Luis A1 - Banerjee, S. A1 - Grass, Eckhard A1 - Krstic, Milos T1 - A 16-Bit CORDIC Rotator for High-Speed Wireless LAN Y1 - 2004 ER - TY - CHAP A1 - Maharatna, Koushik A1 - Troya Chinchilla, Alfonso Luis A1 - Krstic, Milos A1 - Grass, Eckhard A1 - Jagdhold, Ulrich T1 - A CORDIC Like Processor for Computation of Arctangent and Absolute Magnitude of a Vector Y1 - 2004 ER - TY - JOUR A1 - Krstic, Milos A1 - Maharatna, Koushik A1 - Troya Chinchilla, Alfonso Luis A1 - Grass, Eckhard A1 - Jagdhold, Ulrich T1 - Baseband Processor for IEEE 802.11a Standard with embedded BIST Y1 - 2004 ER - TY - CHAP A1 - Krstic, Milos A1 - Grass, Eckhard T1 - GALS Baseband Processor for WLAN Y1 - 2004 ER - TY - CHAP A1 - Stahl, C. A1 - Reisig, W. A1 - Krstic, Milos T1 - Hazard Detection in GALS Wrapper: A Case Study Y1 - 2005 ER - TY - JOUR A1 - Maharatna, Koushik A1 - Banerjee, S. A1 - Grass, Eckhard A1 - Krstic, Milos A1 - Troya Chinchilla, Alfonso Luis T1 - Modified Virtually Scaling Free Adaptive CORDIC Rotator Algorithm and Architecture Y1 - 2005 ER - TY - GEN A1 - Krstic, Milos A1 - Stojčev, M. K. A1 - Djordjevic, Goran L. A1 - Andrejic, I. D. T1 - A Mid Value-Select Voter T2 - Microelectronics Reliability Y1 - 2005 U6 - https://doi.org/10.1016/j.microrel.2004.07.006 SN - 0026-2714 VL - 45 IS - 3/4 SP - 733 EP - 738 ER - TY - CHAP A1 - Krstic, Milos A1 - Grass, Eckhard A1 - Stahl, C. T1 - Request-Driven GALS Technique for Wireless Communication System Y1 - 2005 ER - TY - RPRT A1 - Tittelbach-Helmrich, Klaus A1 - Krstic, Milos A1 - Fiebig, Norbert A1 - Methfessel, Michael T1 - Test Report for WLAN Access Point Chipset, Deliverable D5.2 Y1 - 2005 ER - TY - PAT A1 - Grass, Eckhard A1 - Krstic, Milos A1 - Winkler, F. T1 - GALS-Schaltung und Verfahren zum Betrieb einer GALS-Schaltung Y1 - 2005 ER - TY - CHAP A1 - Grass, Eckhard A1 - Winkler, F. A1 - Krstic, Milos A1 - Julius, A. A1 - Stahl, C. A1 - Piz, M. T1 - Enhanced GALS Techniques for Datapath Applications Y1 - 2005 ER - TY - CHAP A1 - Krstic, Milos A1 - Grass, Eckhard T1 - BIST Testing for GALS Systems Y1 - 2005 ER - TY - GEN A1 - Nikolic, Tatjana A1 - Djordjevic, Goran L. A1 - Krstic, Milos A1 - Stojcev, M. T1 - Data Transfers over Peripheral Bus Using CDMA Technique Y1 - 2011 ER - TY - CHAP A1 - Fan, X. A1 - Krstic, Milos A1 - Wolf, Ch. A1 - Grass, Eckhard T1 - GALS Design for On-Chip Ground Bounce Suppression Y1 - 2011 ER - TY - CHAP A1 - Krstic, Milos A1 - Fan, X. A1 - Grass, Eckhard A1 - Strano, A. A1 - Bertozzi, Davide A1 - Heer, Ch. A1 - Sanders, B. A1 - Benini, L. A1 - Kakooe, M. R. T1 - Moonrake Chip - GALS Demonstrator in 40 nm CMOS Technology Y1 - 2011 ER - TY - CHAP A1 - Simevski, Aleksandar A1 - Kraemer, Rolf A1 - Krstic, Milos T1 - Low-Complexity Integrated Circuit Aging Monitor Y1 - 2011 ER - TY - CHAP A1 - Wolf, Christoph A1 - Zeidler, Steffen A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Overview on ATE Test and Debugging Methods for Asynchronous Circuits Y1 - 2011 ER - TY - CHAP A1 - Schrape, Oliver A1 - Krstic, Milos A1 - Philipp, Gunnar A1 - Winkler, Frank T1 - A Digital Design Flow for Differential ECL High Speed Applications Y1 - 2011 ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - An Analysis of the Operation and SET Robustness of a CMOS Pulse Stretching Circuit T2 - 20thInternational Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2017), 19-21 April 2017 Dresden Y1 - 2017 SN - 978-1-5386-0472-4 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Ilic, Aleksandar A1 - Stamenković, Zoran A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - An Overview of the Current Models for the Circuit-level Simulations of Single Event Transients T2 - Book of abstracts, 5th International Conference on Radiation and Applications in Various Fields of Research (RAD 2017), June 12-16, 2017, Budva, Montenegro Y1 - 2017 SP - S. 184 ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Ilic, Aleksandar A1 - Stamenković, Zoran A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - An Overview of the Modeling and Simulation of the Single Event Transients at the Circuit Level T2 - 30th International Conference on Microelectronics (MIEL), 9-11 Oct. 2017, Nis, Serbia Y1 - 2017 SN - 978-1-5386-2563-7 SN - 978-1-5386-2561-3 U6 - https://doi.org/10.1109/MIEL.2017.8190065 SP - 35 EP - 44 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Assessment of the Amplitude-duration Criterion for SET Robusness Evaluation T2 - 23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Thessaloniki, Greece, 3-5 July 2017 Y1 - 2017 SN - 978-1-5386-0352-9 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Simevski, Aleksandar A1 - Schleisiek, Klaus A1 - Petrovic, Vladimir A1 - Beller, Norbert A1 - Skoncej, Patryk A1 - Schoof, Gunther A1 - Krstic, Milos T1 - Implementation of a Real Time Unit for Satellite Applications T2 - 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 20-22 April 2016, Kosice, Slovakia Y1 - 2016 SN - 978-1-5090-2467-4 SP - 180 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Krstic, Milos A1 - Fan, Xin A1 - Babic, Milan A1 - Grass, Eckhard A1 - Bjerregaard, T. A1 - Yakovlev, A. T1 - Reducing Switching Noise Effects by Advanced Clock Management T2 - 11th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo), 4-8 July, St. Petersburg, Russia 2017 Y1 - 2017 SN - 978-1-5386-2689-4 SP - 3 EP - 8 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Babic, Milan A1 - Zeidler, Steffen A1 - Krstic, Milos T1 - GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated Circuits T2 - 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2016), 8-11 May, Porto Alegre, Brazil, 2016 Y1 - 2016 SN - 978-1-4673-9007-1 SP - 67 EP - 74 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Petrovic, Vladimir A1 - Nenadovic, Miljana A1 - Breitenreiter, Anselm A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Design of an On-Chip System for the SET Pulse Width Measurement T2 - Euromicro Conference on Digital System Design, 30 Aug.-1 Sept., Vienna, Austria 2017 Y1 - 2017 SN - 978-1-5386-2146-2 SP - 111 EP - 118 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Krstic, Milos A1 - Kraemer, Rolf A1 - Veeravalli, Varadan Savulimedu A1 - Steininger, Andreas T1 - Erstellung eines Modells der kritischen Ladung zur Bewertung der Robustheit gegenüber SETs und SEUs: Fallstudie Muller C-Element T2 - Zuverlässigkeit und Entwurf, 9. ITG/GMM/GI-Fachtagung vom 18.-20. September 2017 in Cottbus Y1 - 2017 SN - 978-3-8007-4444-2 SP - 17 EP - 24 PB - Berlin CY - VDE Verlag ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Nenadovic, Miljana A1 - Petrovic, Vladimir A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Evaluation of the Pulse Stretcher for Detection of Very Short Single Event Transients T2 - Book of abstracts, 5th International Conference on Radiation and Applications in Various Fields of Research (RAD 2017), Budva, Montenegro, 2017 Y1 - 2017 UR - http://rad2017.rad-conference.org/news.php SP - S. 214 ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Comparison of the SET Sensitivity of Standard Logic Gates Designed in 130 nm CMOS Technology T2 - 30th International Conference on Microelectronics (MIEL), 9-11 Oct. 2017, Nis, Serbia Y1 - 2017 SN - 978-1-5386-2563-7 SN - 978-1-5386-2561-3 U6 - https://doi.org/10.1109/MIEL.2017.8190106 SP - 217 EP - 220 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Jagdhold, Ulrich A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - 2D TCAD Simulation of Single Event Transients in 250 nm Bulk CMOS Technology T2 - Zuverlässigkeit und Entwurf, 9. ITG/GMM/GI-Fachtagung vom 18.-20. September 2017 in Cottbus Y1 - 2017 SN - 978-3-8007-4444-2 SP - 90 EP - 96 PB - Berlin CY - VDE Verlag ER - TY - CHAP A1 - Babic, Milan A1 - Krstic, Milos T1 - A Substrate Noise Reduction Methodology Based on Power Domain Separation of GALS Subcomponents T2 - 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), September 25-27, 2017, Aristotle University Research Dissemination Center (KEDEA), Thessaloniki, Greece Y1 - 2017 SN - 978-1-5090-6462-5 U6 - https://doi.org/10.1109/PATMOS.2017.8106981 SP - 6 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Babic, Milan A1 - Krstic, Milos T1 - GALS Methodology for Substrate Noise Reduction in BiCMOS Technologies T2 - Proceedings, Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN), Tallinn, Estonia, 2015 Y1 - 2015 UR - http://www.median-project.eu/wp-content/uploads/MEDIAN-Finale-s2-3.pdf ER - TY - CHAP A1 - Babic, Milan A1 - Krstic, Milos T1 - A Coarse Model for Estimation of Switching Noise Coupling in Lightly Doped Substrates T2 - 18th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Belgrade, Serbia, 2015 Y1 - 2015 SN - 978-1-4799-6780-3 SN - 978-1-4799-6779-7 SP - 217 EP - 222 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Babic, Milan A1 - Fan, Xin A1 - Krstic, Milos T1 - Frequency-Domain Modeling of Ground Bounce and Substrate Noise for Synchronous and GALS Systems T2 - 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 1-4 Sept. Salvador, Brazil 2015 Y1 - 2015 SN - 978-1-4673-9419-2 SP - 126 EP - 132 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Krstic, Milos A1 - Kraemer, Rolf A1 - Veeravalli, Varadan Savulimedu A1 - Steininger, Andreas T1 - A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study T2 - IEEE 26th Asian Test Symposium (ATS), Taipei, Taiwan, 28-30 November 2017 Y1 - 2017 SN - 978-1-5386-2437-1 U6 - https://doi.org/10.1109/ATS.2017.27 SP - 78 EP - 83 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Stamenković, Zoran A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Impact of Resistive Open and Bridge Defects on the SET Robustness of CMOS Combinational Logic T2 - IEEE East-West Design & Test Symposium (EWDTS 2018), Kazan, Russia, 14 - 17 September 2018 Y1 - 2018 SN - 978-1-5386-5709-6 U6 - https://doi.org/10.1109/EWDTS.2018.8524748 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Andjelkovic, Marko A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Study of the Operation and SET Robustness of a CMOS Pulse Stretching Circuit T2 - Microelectronics Reliability Y1 - 2018 U6 - https://doi.org/10.1016/j.microrel.2017.12.022 SN - 0026-2714 SN - 1872-941X VL - 82 SP - 100 EP - 112 ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Babic, Milan A1 - Li, Yuanqing A1 - Schrape, Oliver A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Use of Decoupling Cells for Mitigation of SET Effects in CMOS Combinational Gates T2 - 25th IEEE International Conference on Electronics Circuits and Systems (ICECS 2018), Bordeaux, France, 09 - 12 December 2018 Y1 - 2018 SN - 978-1-5386-9562-3 SN - 978-1-5386-9116-8 U6 - https://doi.org/10.1109/ICECS.2018.8617996 SP - 361 EP - 364 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Segabinazzi Ferreira, Raphael A1 - George, Nevin A1 - Chen, Junchao A1 - Hübner, Michael A1 - Krstic, Milos A1 - Nolte, Jörg A1 - Vierhaus, Heinrich Theodor T1 - Configurable Fault Tolerant Circuits and System Level Integration for Self-Awareness T2 - Proceedings of the Work in Progress Session held in connection with SEAA 2019, the 45th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2019, the 22nd EUROMICRO Conference on Digital System Design N2 - Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on- line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system. Y1 - 2019 SN - 978-3-902457-54-7 U6 - https://doi.org/10.26127/BTUOpen-5050 PB - SEA-Publications CY - Kallithea, Chalkidiki (Greece) ER - TY - GEN A1 - Andjelkovic, Marko A1 - Li, Yuanqing A1 - Stamenković, Zoran A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Characterization and Modeling of SET Generation Effects in CMOS Standard Logic Cells T2 - 25th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2019), Rhodos, Greece, 01 - 03 July 2019 Y1 - 2019 SN - 978-1-7281-2490-2 SN - 978-1-7281-2489-6 SN - 978-1-7281-2491-9 U6 - https://doi.org/10.1109/IOLTS.2019.8854379 SN - 1942-9401 PB - IEEE ER - TY - GEN A1 - Veleski, Mitko A1 - Kraemer, Rolf A1 - Krstic, Milos T1 - SWIELD: An In Situ Approach for Adaptive Low Power and Error-Resilient Operation T2 - 17th IEEE East-West Design & Test Symposium (EWDTS 2019), Batumi, Georgia, 13 - 16 September 2019 Y1 - 2019 SN - 978-1-7281-1003-5 SN - 978-1-7281-1002-8 SN - 978-1-7281-1004-2 U6 - https://doi.org/10.1109/EWDTS.2019.8884428 SN - 2472-761X PB - IEEE ER - TY - GEN A1 - Jenihhin, Maksim A1 - Hamdioui, Said A1 - Sonza-Reorda, Matteo A1 - Krstic, Milos A1 - Langendörfer, Peter A1 - Sauer, Christian A1 - Klotz, Anton A1 - Hübner, Michael A1 - Nolte, Jörg A1 - Vierhaus, Heinrich Theodor A1 - Selimis, Georgions A1 - Alexandrescu, Dan A1 - Taouil, Mottaqiallah A1 - Schrijen, Geert-Jan A1 - Sterpone, Luca A1 - Squillero, Giovanni A1 - Dyka, Zoya A1 - Raik, Jaan T1 - RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems T2 - ArXiv.org Y1 - 2019 UR - https://arxiv.org/abs/1912.01561 ER - TY - GEN A1 - Veleski, Mitko A1 - Kraemer, Rolf A1 - Krstic, Milos T1 - A Programmable Error-Predictive In-Situ Delay Monitor for Adaptive Low Power and Error-Resilient Complex System-On-Chip T2 - 9th Biannual European - Latin American Summer School on Design, Test and Reliability (BELAS 2019), Frankfurt/Oder Y1 - 2019 UR - https://www.ihp-microelectronics.com/en/research/wireless-systems-and-applications/publications/publications-2019.html ER - TY - GEN A1 - Veleski, Mitko A1 - Kraemer, Rolf A1 - Krstic, Milos T1 - Programmable In-Situ Delay Monitor for Energy-Efficient and Resilient Complex SoC T2 - Proc. 24th IEEE European Test Symposium: PhD Forum (ETS 2019) Y1 - 2019 UR - https://www.ihp-microelectronics.com/en/research/wireless-systems-and-applications/publications/publications-2019.html ER - TY - GEN A1 - Veleski, Mitko A1 - Kraemer, Rolf A1 - Krstic, Milos T1 - The Effects of Voltage Scaling on Reliability and Power Consumption in Multiprocessor Systems T2 - Proc. 30. GI/GMM/ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2018), 38 (2018) Y1 - 2018 UR - https://www.ihp-microelectronics.com/en/research/wireless-systems-and-applications/publications/publications-2018.html ER - TY - GEN A1 - Veleski, Mitko A1 - Kraemer, Rolf A1 - Krstic, Milos T1 - An Overview of Cross-Layer Resilience Design Methods T2 - RESCUE 2017, Limassol Y1 - 2017 UR - https://www.researchgate.net/publication/349116576_An_Overview_of_Cross-Layer_Resilience_Design_Methods ER - TY - GEN A1 - Andjelkovic, Marko A1 - Veleski, Mitko A1 - Chen, Junchao A1 - Simevski, Aleksandar A1 - Krstic, Milos T1 - A Particle Detector Based on Pulse Stretching Inverter Chain T2 - 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2019), Genova Y1 - 2019 SN - 978-1-7281-0996-1 SN - 978-1-7281-0997-8 U6 - https://doi.org/10.1109/ICECS46596.2019.8964644 ER - TY - GEN A1 - Andjelkovic, Marko A1 - Chen, Junchao A1 - Simevski, Aleksandar A1 - Stamenkovic, Zoran A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - A Review of Particle Detectors for Space-Borne Self-Adaptive Fault Tolerant Systems T2 - 18th IEEE East-West Design and Test Symposium (EWDTS 2020), Varna, Bulgaria, 04 - 07 September 2020 Y1 - 2020 SN - 978-1-7281-9899-6 SN - 978-1-7281-9898-9 SN - 978-1-7281-9900-9 U6 - https://doi.org/10.1109/EWDTS50664.2020.9225138 SN - 2472-761X PB - IEEE ER - TY - GEN A1 - Veleski, Mitko A1 - Hübner, Michael A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Highly Configurable Framework for Adaptive Low Power and Error-Resilient System-On-Chip T2 - 23rd EUROMICRO Conference on Digital System Design (DSD 2020), Portoroz, Slovenia, 26 - 28 August 2020 Y1 - 2020 SN - 978-1-7281-9535-3 SN - 978-1-7281-9536-0 U6 - https://doi.org/10.1109/DSD51259.2020.00015 SP - 24 EP - 28 PB - IEEE ER - TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Pérez, Eduardo A1 - Ulbricht, Markus A1 - Wenger, Christian A1 - Krstic, Milos T1 - Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages T2 - 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) N2 - RRAM technology is a promising candidate for implementing efficient AI accelerators with extensive multiply-accumulate operations. By scaling RRAM devices to the synaptic crossbar array, the computations can be realized in situ, avoiding frequent weights transfer between the processing units and memory. Besides, as the computations are conducted in the analog domain with high flexibility, applying multilevel input voltages to the RRAM devices with multilevel conductance states enhances the computational efficiency further. However, several non-idealities existing in emerging RRAM technology may degrade the reliability of the system. In this paper, we measured and investigated the impact of read disturb on RRAM devices with different input voltages, which incurs conductance drifts and introduces errors. The measured data are deployed to simulate the RRAM based AI inference engines with multilevel states. KW - RRAM KW - Multilevel switching KW - AI accelarator Y1 - 2022 SN - 978-1-6654-5938-9 SN - 978-1-6654-5937-2 U6 - https://doi.org/10.1109/DFT56152.2022.9962345 SN - 2765-933X SP - 1 EP - 6 ER - TY - GEN A1 - Veleski, Mitko A1 - Hübner, Michael A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Design and implementation strategy of adaptive processor-based systems for error resilient and power-efficient operation T2 - 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS, April 7-9 2021 Y1 - 2021 SN - 978-1-6654-3595-6 U6 - https://doi.org/10.1109/DDECS52668.2021.9417023 SP - 57 EP - 62 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Veleski, Mitko A1 - Hübner, Michael A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Towards Error Resilient and Power-Efficient Adaptive Multiprocessor System using Highly Configurable and Flexible Cross-Layer Framework T2 - IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS), IOLTS 2021, June 28-30, 2021 Y1 - 2021 SN - 978-1-6654-3370-9 U6 - https://doi.org/10.1109/IOLTS52814.2021.9486695 SP - 1 EP - 7 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Wen, Jianan A1 - Vargas, Fabian Luis A1 - Zhu, Fukun A1 - Reiser, Daniel A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Pérez, Eduardo A1 - Reichenbach, Marc A1 - Wenger, Christian A1 - Krstic, Milos T1 - Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment T2 - 2024 IEEE 25th Latin American Test Symposium (LATS) N2 - Emerging device technologies such as resistive RAM (RRAM) are increasingly recognized in enhancing system performance, particularly in applications demanding extensive vector-matrix multiplications (VMMs) with high parallelism. However, a significant limitation in current electronics design automation (EDA) tools is their lack of support for rapid prototyping, design space exploration, and the integration of inherent process-dependent device variability into system-level simulations, which is essential for assessing system reliability. To address this gap, we introduce a field-programmable gate array (FPGA) based emulation approach for RRAM crossbars featuring cycle-accurate emulations in real time without relying on complex device models. Our approach is based on pre-generated look-up tables (LUTs) to accurately represent the RRAM device behavior. To efficiently model the device variability at the system level, we propose using the multivariate kernel density estimation (KDE) method to augment the measured RRAM data. The proposed emulator allows precise latency determination for matrix mapping and computation operations. Meanwhile, by coupling with the NeuroSim framework, the corresponding energy consumption can be estimated. In addition to facilitating a range of in-depth system assessments, experimental results suggest a remarkable reduction of emulation time compared to the classic behavioral simulation. KW - RRAM Y1 - 2024 U6 - https://doi.org/10.1109/LATS62223.2024.10534601 PB - IEEE ER - TY - GEN A1 - Fritscher, Markus A1 - Singh, Simranjeet A1 - Rizzi, Tommaso A1 - Baroni, Andrea A1 - Reiser, Daniel A1 - Mallah, Maen A1 - Hartmann, David A1 - Bende, Ankit A1 - Kempen, Tim A1 - Uhlmann, Max A1 - Kahmen, Gerhard A1 - Fey, Dietmar A1 - Rana, Vikas A1 - Menzel, Stephan A1 - Reichenbach, Marc A1 - Krstic, Milos A1 - Merchant, Farhad A1 - Wenger, Christian T1 - A flexible and fast digital twin for RRAM systems applied for training resilient neural networks T2 - Scientific Reports N2 - Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the “ideal memristor” which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a “push button” modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT). KW - RRAM KW - Neural network KW - digital twin Y1 - 2024 U6 - https://doi.org/10.1038/s41598-024-73439-z SN - 2045-2322 VL - 14 IS - 1 PB - Springer Science and Business Media LLC ER - TY - GEN A1 - Fritscher, Markus A1 - Wenger, Christian A1 - Krstic, Milos T1 - From device to application - integrating RRAM Accelerator Blocks into large AI systems T2 - 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) N2 - This work provides an introduction to design methodologies for RRAM-based systems. We illustrate the impact of device variation on the performance of neural networks and propose a circuit-level integration approach for RRAM-based compute blocks. Moreover, we demonstrate a possible architectural integration by incorporating RRAM-based VMM blocks fabricated in a 130 nm CMOS process into a RISC-V. KW - RRAM Y1 - 2024 SN - 979-8-3503-5411-9 SN - 979-8-3503-5412-6 U6 - https://doi.org/10.1109/ISVLSI61997.2024.00111 SN - 2159-3477 SP - 592 EP - 592 PB - IEEE ER - TY - GEN A1 - Fritscher, Markus A1 - Uhlmann, Max A1 - Ostrovskyy, Philip A1 - Reiser, Daniel A1 - Chen, Junchao A1 - Schubert, Andreas A1 - Schulze, Carsten A1 - Kahmen, Gerhard A1 - Fey, Dietmar A1 - Reichenbach, Marc A1 - Krstic, Milos A1 - Wenger, Christian T1 - Area-efficient digital design using RRAM-CMOS standard cells T2 - 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) N2 - Extending the scalability of digital integrated circuits through novel device concepts is an attractive option. Among these concepts, resistive random access memory (RRAM) devices allow fast and nonvolatile operation. However, building large memristive systems is still challenging since large analog circuits have to be designed and integrated. In this paper, we propose a novel solution - the implementation of digital standard cells by the means of RRAM devices. While this methodology is universal, with applications ranging from few-device-circuits to large macroblocks, we demonstrate it for a 2T2R-cell. The benefits of using RRAM devices are demonstrated by implementing a NAND standard cell merely consuming the area of two transistors. This cell is about 25 % smaller than the equivalent CMOS NAND in the same technology. We use these cells to implement a half adder, beating the area of the equivalent CMOS implementation using more sophisticates gates by 15 %. Lastly, we fully integrate this novel standard cell into a digital standard cell library and perform a synthesis and layout of a RISC-V CPU core. KW - RRAM Y1 - 2024 SN - 979-8-3503-5411-9 SN - 979-8-3503-5412-6 U6 - https://doi.org/10.1109/ISVLSI61997.2024.00026 SN - 2159-3477 VL - 18 SP - 81 EP - 87 PB - IEEE ER - TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Perez, Eduardo A1 - Uhlmann, Max A1 - Fritscher, Markus A1 - KrishneGowda, Karthik A1 - Ulbricht, Markus A1 - Wenger, Christian A1 - Krstic, Milos T1 - Towards reliable and energy-efficient RRAM based discrete fourier transform accelerator T2 - 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) N2 - The Discrete Fourier Transform (DFT) holds a prominent place in the field of signal processing. The development of DFT accelerators in edge devices requires high energy efficiency due to the limited battery capacity. In this context, emerging devices such as resistive RAM (RRAM) provide a promising solution. They enable the design of high-density crossbar arrays and facilitate massively parallel and in situ computations within memory. However, the reliability and performance of the RRAM-based systems are compromised by the device non-idealities, especially when executing DFT computations that demand high precision. In this paper, we propose a novel adaptive variability-aware crossbar mapping scheme to address the computational errors caused by the device variability. To quantitatively assess the impact of variability in a communication scenario, we implemented an end-to-end simulation framework integrating the modulation and demodulation schemes. When combining the presented mapping scheme with an optimized architecture to compute DFT and inverse DFT(IDFT), compared to the state-of-the-art architecture, our simulation results demonstrate energy and area savings of up to 57 % and 18 %, respectively. Meanwhile, the DFT matrix mapping error is reduced by 83% compared to conventional mapping. In a case study involving 16-quadrature amplitude modulation (QAM), with the optimized architecture prioritizing energy efficiency, we observed a bit error rate (BER) reduction from 1.6e-2 to 7.3e-5. As for the conventional architecture, the BER is optimized from 2.9e-3 to zero. KW - RRAM Y1 - 2024 SN - 978-3-9819263-8-5 SN - 979-8-3503-4860-6 U6 - https://doi.org/10.23919/DATE58400.2024.10546709 SN - 1558-1101 SP - 1 EP - 6 PB - IEEE ER - TY - GEN A1 - Perez-Bosch Quesada, Emilio A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Rizzi, Tommaso A1 - Wen, Jianan A1 - Ulbricht, Markus A1 - Krstic, Milos A1 - Wenger, Christian A1 - Pérez, Eduardo T1 - Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing T2 - IEEE Transactions on Electron Devices N2 - Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of 8x8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices’ nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems. KW - RRAM KW - Vector Matrix Multiplication KW - variability Y1 - 2023 U6 - https://doi.org/10.1109/TED.2023.3244509 SN - 0018-9383 VL - 70 IS - 4 SP - 2009 EP - 2014 ER - TY - GEN A1 - Dyka, Zoya A1 - Kabin, Ievgen A1 - Brzozowski, Marcin A1 - Panic, Goran A1 - Calligaro, Cristiano A1 - Krstic, Milos A1 - Langendörfer, Peter T1 - On the SCA Resistance of Crypto IP Cores T2 - 23rd IEEE Latin-American Test Symposium (LATS 2022), Montevideo, Uruguay, 05-08 September 2022 Y1 - 2022 SN - 978-1-6654-5707-1 SN - 978-1-6654-5708-8 U6 - https://doi.org/10.1109/LATS57337.2022.9937007 SN - 2373-0862 ER - TY - GEN A1 - Wen, Jianan A1 - Vargas, Fabian Luis A1 - Zhu, Fukun A1 - Reiser, Daniel A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Perez, Eduardo A1 - Reichenbach, Marc A1 - Wenger, Christian A1 - Krstic, Milos T1 - RRAMulator : an efficient FPGA-based emulator for RRAM crossbar with device variability and energy consumption evaluation T2 - Microelectronics Reliability N2 - The in-memory computing (IMC) systems based on emerging technologies have gained significant attention due to their potential to enhance performance and energy efficiency by minimizing data movement between memory and processing unit, which is especially beneficial for data-intensive applications. Designing and evaluating systems utilizing emerging memory technologies, such as resistive RAM (RRAM), poses considerable challenges due to the limited support from electronics design automation (EDA) tools for rapid development and design space exploration. Additionally, incorporating technology-dependent variability into system-level simulations is critical to accurately assess the impact on system reliability and performance. To bridge this gap, we propose RRAMulator, a field-programmable gate array (FPGA) based hardware emulator for RRAM crossbar array. To avoid the complex device models capturing the nonlinear current–voltage (IV) relationships that degrade emulation speed and increase hardware utilization, we propose a device and variability modeling approach based on device measurements. We deploy look-up tables (LUTs) for device modeling and use the multivariate kernel density estimation (KDE) method to augment existing data, extending data variety and avoiding repetitive data usage. The proposed emulator achieves cycle-accurate, real-time emulations and provides information such as latency and energy consumption for matrix mapping and vector–matrix multiplications (VMMs). Experimental results show a significant reduction in emulation time compared to conventional behavioral simulations. Additionally, an RRAM-based discrete Fourier transform (DFT) accelerator is analyzed as a case study featuring a range of in-depth system assessments. KW - RRAM Y1 - 2025 U6 - https://doi.org/10.1016/j.microrel.2025.115630 SN - 0026-2714 VL - 168 SP - 1 EP - 10 PB - Elsevier BV CY - Amsterdam ER - TY - GEN A1 - Fritscher, Markus A1 - Uhlmann, Max A1 - Ostrovskyy, Philip A1 - Reiser, Daniel A1 - Chen, Junchao A1 - Wen, Jianan A1 - Schulze, Carsten A1 - Kahmen, Gerhard A1 - Fey, Dietmar A1 - Reichenbach, Marc A1 - Krstic, Milos A1 - Wenger, Christian ED - Wenger, Christian T1 - RISC-V CPU design using RRAM-CMOS standard cells T2 - IEEE transactions on very large scale integration (VLSI) systems N2 - The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely, creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks, we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors, this enables us to construct a nand standard cell, which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS nand gate. We illustrate achievable area savings with a half-adder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates. KW - RRAM KW - Logic gates Y1 - 2025 UR - https://ieeexplore.ieee.org/document/10960690 U6 - https://doi.org/10.1109/TVLSI.2025.3554476 SN - 1063-8210 SP - 1 EP - 9 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York ER - TY - GEN A1 - Dyka, Zoya A1 - Kabin, Ievgen A1 - Brzozowski, Marcin A1 - Panic, Goran A1 - Calligaro, Cristiano A1 - Krstic, Milos A1 - Langendoerfer, Peter T1 - On the influence of cell libraries and other parameters to SCA resistance of crypto IP cores T2 - 2024 13th Mediterranean Conference on Embedded Computing (MECO) N2 - The ever-growing complexity of modern systems as well as the shrinking time to market enforces the use of already designed hardware components i.e. hard and soft IP cores. The fact that also requirements with respect to security significantly increased and that side-channel analysis (SCA) attacks are meanwhile a well-known threat it is paramount to ensure SCA resistance of ASICs and FPGA implementations derived from cryptographic IP cores. This requires to evaluate this feature for each IP core and target technology even down to the level of the cell library. The experiments reported here clearly show that the three available cell libraries even though developed for the same 130nm technology of IHP exhibit different sensitivity to SCA attacks ranging from quite resistant to very vulnerable. KW - Cryptographic IP cores KW - Elliptic curve cryptography (ECC) KW - Side-channel analysis (SCA) attacks KW - SCA resistance KW - Differential power analysis (DPA) KW - Horizontal attacks Y1 - 2024 SN - 979-8-3503-8756-8 U6 - https://doi.org/10.1109/MECO62516.2024.10577776 SP - 1 EP - 5 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Uhlmann, Max A1 - Perez, Eduardo A1 - Wenger, Christian A1 - Krstic, Milos T1 - ReFFT : an energy-efficient RRAM-based FFT accelerator T2 - IEEE transactions on computer-aided design of integrated circuits and systems N2 - The fast Fourier transform (FFT) is a highly efficient algorithm for computing the discrete Fourier transform (DFT). It is widely employed in various applications, including digital communication, image processing, and signal analysis. Recently, in-memory computing architectures based on emerging technologies, such as resistive RAM (RRAM), have demonstrated promising performance with low hardware cost for data-intensive applications. However, directly mapping FFT onto RRAM crossbars is challenging because the algorithm relies on many small, sequential butterfly operations, while cross-bars are optimized for large-scale, highly parallel vector–matrix multiplications (VMMs). In this paper, we introduce ReFFT, a system architecture that reformulates FFT computations for efficient execution on RRAM crossbars. ReFFT combines the reduced computational complexity of FFT with the parallel VMM capability of RRAM. We incorporate measured device data into our framework to analyze the effect of variability and develop an adaptive mapping scheme that improves twiddle-factor programming accuracy, leading to a 9.9 dB peak signal-to-noise ratio (PSNR) improvement for a 256-point FFT. Compared with prior RRAM-based DFT designs, ReFFT achieves up to 4.6× and 19.5× higher energy efficiency for 256- and 2048-point FFTs, respectively. The system is further validated in digital communication and satellite image compression tasks. KW - RRAM KW - Accelerator Y1 - 2025 U6 - https://doi.org/10.1109/TCAD.2025.3627146 SN - 0278-0070 SP - 1 EP - 14 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Mistroni, Alberto A1 - Perez, Eduardo A1 - Zambelli, Cristian A1 - Wenger, Christian A1 - Krstic, Milos A1 - Bolzani Pöhls, Leticia Maria T1 - ReDiM : an efficient strategy for read disturb mitigation in RRAM-based accelerators T2 - 2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS) N2 - Resistive RAM (RRAM) has emerged as a promising non-volatile memory technology for implementing energy-efficient hardware accelerators within the in-memory computing (IMC) paradigm. However, due to the immature fabrication process and inherent material instabilities, frequent read operations during computations can induce read disturb effects, leading to unintended resistance drift and potential data corruption. Existing mitigation approaches primarily focus on detecting read disturb effects and triggering memory refresh operations. In this work, we propose an architecture-level solution that mitigates read disturb in RRAM-based accelerators. Our strategy employs crossbar duplication and decomposes the single high input pulse into two lower-amplitude pulses, effectively minimizing the risk of read disturb. To validate our approach, we develop a simulation framework that incorporates measurement data from characterized RRAM devices under read disturb stress conditions. Experimental results on VGG-8 with CIFAR-10 demonstrate that the proposed method significantly mitigates inference accuracy degradation caused by read disturb in RRAM-based accelerators, while incurring modest area and energy overheads of 12.32% and 2.15%, respectively. This work provides a practical and scalable solution for enhancing the robustness of RRAM-based accelerators in edge and high-performance computing applications. KW - RRAM KW - Resistive RAM KW - In-memory Computing KW - AI Accelerator KW - Read Disturb KW - Reliability Y1 - 2025 SN - 979-8-3315-3334-2 U6 - https://doi.org/10.1109/IOLTS65288.2025.11117065 SP - 1 EP - 7 PB - IEEE CY - Piscataway, NJ ER -