TY - GEN A1 - Krstic, Milos A1 - Krol, T. A1 - Grass, Eckhard T1 - Reducing EMI using GALS Approach Y1 - 2010 ER - TY - CHAP A1 - Bertozzi, Davide A1 - Strano, A. A1 - Ludovici, D. A1 - Pavlidis, V. A1 - Angiolini, F. A1 - Krstic, Milos T1 - The Synchronization Challenge Y1 - 2010 ER - TY - CHAP A1 - Zeidler, Steffen A1 - Bystrov, Alexander A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - On-line Testing of Bundled-Data Asynchronous Handshake Protocols Y1 - 2010 ER - TY - CHAP A1 - Fan, X. A1 - Krstic, Milos A1 - Grass, Eckhard A1 - Wolf, Ch. T1 - A GALS FFT Processor with Clock Modulation for Low-EMI Applications Y1 - 2010 ER - TY - CHAP A1 - Elvira, Victor A1 - Ibáñez, Jesús A1 - Santamaria, I. A1 - Krstic, Milos A1 - Tittelbach-Helmrich, Klaus A1 - Stamenković, Zoran T1 - Baseband Processor for RF-MIMO WLAN Y1 - 2010 ER - TY - CHAP A1 - Stamenković, Zoran A1 - Tittelbach-Helmrich, Klaus A1 - Krstic, Milos A1 - Ibáñez, Jesús A1 - Elvira, Victor A1 - Santamaria, I. T1 - MAC and Baseband Hardware Platforms for RF-MIMO WLAN Y1 - 2010 ER - TY - CHAP A1 - Stamenković, Zoran A1 - Tittelbach-Helmrich, Klaus A1 - Krstic, Milos A1 - Perez, J. A1 - Via, J. A1 - Ibáñez, Jesús T1 - Architecture of an Analog Combining MIMO System Compliant to IEEE 802.11a Y1 - 2009 ER - TY - CHAP A1 - Miletic, E. A1 - Krstic, Milos A1 - Piz, M. A1 - Methfessel, Michael T1 - Digital Automatic Gain Control Integrated on WLAN Platform Y1 - 2008 ER - TY - CHAP A1 - Fan, X. A1 - Krstic, Milos A1 - Grass, Eckhard T1 - Analysis and Optimization of Pausible Clocking Based GALS Design Y1 - 2009 ER - TY - CHAP A1 - Krol, T. A1 - Krstic, Milos A1 - Fan, X. A1 - Grass, Eckhard T1 - GALS Systems Applied for EMI Reduction Y1 - 2009 ER - TY - CHAP A1 - Zeidler, Steffen A1 - Ehrig, Marcus A1 - Krstic, Milos A1 - Augustin, Michael A1 - Wolf, Christoph A1 - Kraemer, Rolf T1 - Ultra Low Cost Asynchronous Handshake Checker Y1 - 2009 ER - TY - GEN A1 - Krstic, Milos A1 - Fan, X. A1 - Grass, Eckhard A1 - Gürkaynak, F. T1 - GALS for Bursty Data Transfer Based on the Clock Coupling Y1 - 2009 ER - TY - CHAP A1 - Krstic, Milos A1 - Piz, M. A1 - Ehrig, Marcus A1 - Grass, Eckhard T1 - OFDM Datapath Baseband Processor for 1 Gbps Datarate Y1 - 2008 ER - TY - PAT A1 - Fan, X. A1 - Krstic, Milos A1 - Grass, Eckhard T1 - Aussetzbarer Taktgenerator Y1 - 2008 ER - TY - PAT A1 - Krstic, Milos A1 - Grass, Eckhard T1 - GALS-Schaltung mit arbitriertem eingangs- und ausgangsseitigem Taktantrieb Y1 - 2007 ER - TY - CHAP A1 - Krstic, Milos A1 - Grass, Eckhard A1 - Stahl, C. T1 - Request-Driven GALS Technique for Wireless Communication System Y1 - 2005 ER - TY - CHAP A1 - Krstic, Milos A1 - Grass, Eckhard T1 - BIST Testing for GALS Systems Y1 - 2005 ER - TY - CHAP A1 - Krstic, Milos A1 - Grass, Eckhard T1 - GALSification of IEEE 802.11a Baseband Processor Y1 - 2004 ER - TY - CHAP A1 - Maharatna, Koushik A1 - Troya Chinchilla, Alfonso Luis A1 - Banerjee, S. A1 - Grass, Eckhard A1 - Krstic, Milos T1 - A 16-Bit CORDIC Rotator for High-Speed Wireless LAN Y1 - 2004 ER - TY - CHAP A1 - Krstic, Milos A1 - Grass, Eckhard T1 - GALS Baseband Processor for WLAN Y1 - 2004 ER - TY - CHAP A1 - Stahl, C. A1 - Reisig, W. A1 - Krstic, Milos T1 - Hazard Detection in GALS Wrapper: A Case Study Y1 - 2005 ER - TY - JOUR A1 - Maharatna, Koushik A1 - Banerjee, S. A1 - Grass, Eckhard A1 - Krstic, Milos A1 - Troya Chinchilla, Alfonso Luis T1 - Modified Virtually Scaling Free Adaptive CORDIC Rotator Algorithm and Architecture Y1 - 2005 ER - TY - CHAP A1 - Wolf, Christoph A1 - Zeidler, Steffen A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Overview on ATE Test and Debugging Methods for Asynchronous Circuits Y1 - 2011 ER - TY - CHAP A1 - Simevski, Aleksandar A1 - Schleisiek, Klaus A1 - Petrovic, Vladimir A1 - Beller, Norbert A1 - Skoncej, Patryk A1 - Schoof, Gunther A1 - Krstic, Milos T1 - Implementation of a Real Time Unit for Satellite Applications T2 - 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 20-22 April 2016, Kosice, Slovakia Y1 - 2016 SN - 978-1-5090-2467-4 SP - 180 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Babic, Milan A1 - Zeidler, Steffen A1 - Krstic, Milos T1 - GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated Circuits T2 - 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2016), 8-11 May, Porto Alegre, Brazil, 2016 Y1 - 2016 SN - 978-1-4673-9007-1 SP - 67 EP - 74 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Babic, Milan A1 - Krstic, Milos T1 - A Coarse Model for Estimation of Switching Noise Coupling in Lightly Doped Substrates T2 - 18th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Belgrade, Serbia, 2015 Y1 - 2015 SN - 978-1-4799-6780-3 SN - 978-1-4799-6779-7 SP - 217 EP - 222 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Babic, Milan A1 - Fan, Xin A1 - Krstic, Milos T1 - Frequency-Domain Modeling of Ground Bounce and Substrate Noise for Synchronous and GALS Systems T2 - 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 1-4 Sept. Salvador, Brazil 2015 Y1 - 2015 SN - 978-1-4673-9419-2 SP - 126 EP - 132 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Babic, Milan A1 - Krstic, Milos T1 - GALS Methodology for Substrate Noise Reduction in BiCMOS Technologies T2 - Proceedings, Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN), Tallinn, Estonia, 2015 Y1 - 2015 UR - http://www.median-project.eu/wp-content/uploads/MEDIAN-Finale-s2-3.pdf ER - TY - GEN A1 - Andjelkovic, Marko A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Study of the Operation and SET Robustness of a CMOS Pulse Stretching Circuit T2 - Microelectronics Reliability Y1 - 2018 U6 - https://doi.org/10.1016/j.microrel.2017.12.022 SN - 0026-2714 SN - 1872-941X VL - 82 SP - 100 EP - 112 ER - TY - GEN A1 - Segabinazzi Ferreira, Raphael A1 - George, Nevin A1 - Chen, Junchao A1 - Hübner, Michael A1 - Krstic, Milos A1 - Nolte, Jörg A1 - Vierhaus, Heinrich Theodor T1 - Configurable Fault Tolerant Circuits and System Level Integration for Self-Awareness T2 - Proceedings of the Work in Progress Session held in connection with SEAA 2019, the 45th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2019, the 22nd EUROMICRO Conference on Digital System Design N2 - Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on- line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system. Y1 - 2019 SN - 978-3-902457-54-7 U6 - https://doi.org/10.26127/BTUOpen-5050 PB - SEA-Publications CY - Kallithea, Chalkidiki (Greece) ER - TY - GEN A1 - Jenihhin, Maksim A1 - Hamdioui, Said A1 - Sonza-Reorda, Matteo A1 - Krstic, Milos A1 - Langendörfer, Peter A1 - Sauer, Christian A1 - Klotz, Anton A1 - Hübner, Michael A1 - Nolte, Jörg A1 - Vierhaus, Heinrich Theodor A1 - Selimis, Georgions A1 - Alexandrescu, Dan A1 - Taouil, Mottaqiallah A1 - Schrijen, Geert-Jan A1 - Sterpone, Luca A1 - Squillero, Giovanni A1 - Dyka, Zoya A1 - Raik, Jaan T1 - RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems T2 - ArXiv.org Y1 - 2019 UR - https://arxiv.org/abs/1912.01561 ER - TY - GEN A1 - Andjelkovic, Marko A1 - Veleski, Mitko A1 - Chen, Junchao A1 - Simevski, Aleksandar A1 - Krstic, Milos T1 - A Particle Detector Based on Pulse Stretching Inverter Chain T2 - 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2019), Genova Y1 - 2019 SN - 978-1-7281-0996-1 SN - 978-1-7281-0997-8 U6 - https://doi.org/10.1109/ICECS46596.2019.8964644 ER - TY - GEN A1 - Veleski, Mitko A1 - Kraemer, Rolf A1 - Krstic, Milos T1 - A Programmable Error-Predictive In-Situ Delay Monitor for Adaptive Low Power and Error-Resilient Complex System-On-Chip T2 - 9th Biannual European - Latin American Summer School on Design, Test and Reliability (BELAS 2019), Frankfurt/Oder Y1 - 2019 UR - https://www.ihp-microelectronics.com/en/research/wireless-systems-and-applications/publications/publications-2019.html ER - TY - GEN A1 - Veleski, Mitko A1 - Kraemer, Rolf A1 - Krstic, Milos T1 - Programmable In-Situ Delay Monitor for Energy-Efficient and Resilient Complex SoC T2 - Proc. 24th IEEE European Test Symposium: PhD Forum (ETS 2019) Y1 - 2019 UR - https://www.ihp-microelectronics.com/en/research/wireless-systems-and-applications/publications/publications-2019.html ER - TY - GEN A1 - Veleski, Mitko A1 - Kraemer, Rolf A1 - Krstic, Milos T1 - The Effects of Voltage Scaling on Reliability and Power Consumption in Multiprocessor Systems T2 - Proc. 30. GI/GMM/ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2018), 38 (2018) Y1 - 2018 UR - https://www.ihp-microelectronics.com/en/research/wireless-systems-and-applications/publications/publications-2018.html ER - TY - GEN A1 - Veleski, Mitko A1 - Kraemer, Rolf A1 - Krstic, Milos T1 - An Overview of Cross-Layer Resilience Design Methods T2 - RESCUE 2017, Limassol Y1 - 2017 UR - https://www.researchgate.net/publication/349116576_An_Overview_of_Cross-Layer_Resilience_Design_Methods ER - TY - GEN A1 - Veleski, Mitko A1 - Hübner, Michael A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Highly Configurable Framework for Adaptive Low Power and Error-Resilient System-On-Chip T2 - 23rd EUROMICRO Conference on Digital System Design (DSD 2020), Portoroz, Slovenia, 26 - 28 August 2020 Y1 - 2020 SN - 978-1-7281-9535-3 SN - 978-1-7281-9536-0 U6 - https://doi.org/10.1109/DSD51259.2020.00015 SP - 24 EP - 28 PB - IEEE ER - TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Perez, Eduardo A1 - Ulbricht, Markus A1 - Wenger, Christian A1 - Krstic, Milos T1 - Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages T2 - 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) N2 - RRAM technology is a promising candidate for implementing efficient AI accelerators with extensive multiply-accumulate operations. By scaling RRAM devices to the synaptic crossbar array, the computations can be realized in situ, avoiding frequent weights transfer between the processing units and memory. Besides, as the computations are conducted in the analog domain with high flexibility, applying multilevel input voltages to the RRAM devices with multilevel conductance states enhances the computational efficiency further. However, several non-idealities existing in emerging RRAM technology may degrade the reliability of the system. In this paper, we measured and investigated the impact of read disturb on RRAM devices with different input voltages, which incurs conductance drifts and introduces errors. The measured data are deployed to simulate the RRAM based AI inference engines with multilevel states. KW - RRAM KW - Multilevel switching KW - AI accelarator Y1 - 2022 SN - 978-1-6654-5938-9 SN - 978-1-6654-5937-2 U6 - https://doi.org/10.1109/DFT56152.2022.9962345 SN - 2765-933X SP - 1 EP - 6 ER - TY - GEN A1 - Dyka, Zoya A1 - Kabin, Ievgen A1 - Brzozowski, Marcin A1 - Panic, Goran A1 - Calligaro, Cristiano A1 - Krstic, Milos A1 - Langendörfer, Peter T1 - On the SCA Resistance of Crypto IP Cores T2 - 23rd IEEE Latin-American Test Symposium (LATS 2022), Montevideo, Uruguay, 05-08 September 2022 Y1 - 2022 SN - 978-1-6654-5707-1 SN - 978-1-6654-5708-8 U6 - https://doi.org/10.1109/LATS57337.2022.9937007 SN - 2373-0862 ER - TY - CHAP A1 - Babic, Milan A1 - Krstic, Milos T1 - A Substrate Noise Reduction Methodology Based on Power Domain Separation of GALS Subcomponents T2 - 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), September 25-27, 2017, Aristotle University Research Dissemination Center (KEDEA), Thessaloniki, Greece Y1 - 2017 SN - 978-1-5090-6462-5 U6 - https://doi.org/10.1109/PATMOS.2017.8106981 SP - 6 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Krstic, Milos A1 - Fan, Xin A1 - Babic, Milan A1 - Grass, Eckhard A1 - Bjerregaard, T. A1 - Yakovlev, A. T1 - Reducing Switching Noise Effects by Advanced Clock Management T2 - 11th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo), 4-8 July, St. Petersburg, Russia 2017 Y1 - 2017 SN - 978-1-5386-2689-4 SP - 3 EP - 8 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Krstic, Milos A1 - Kraemer, Rolf A1 - Veeravalli, Varadan Savulimedu A1 - Steininger, Andreas T1 - Erstellung eines Modells der kritischen Ladung zur Bewertung der Robustheit gegenüber SETs und SEUs: Fallstudie Muller C-Element T2 - Zuverlässigkeit und Entwurf, 9. ITG/GMM/GI-Fachtagung vom 18.-20. September 2017 in Cottbus Y1 - 2017 SN - 978-3-8007-4444-2 SP - 17 EP - 24 PB - Berlin CY - VDE Verlag ER - TY - CHAP A1 - Troya Chinchilla, Alfonso Luis A1 - Maharatna, Koushik A1 - Krstic, Milos A1 - Grass, Eckhard A1 - Kraemer, Rolf T1 - OFDM Synchronizer Implementation for an IEEE 802.11a Compliant Modem Y1 - 2002 ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Jagdhold, Ulrich A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - 2D TCAD Simulation of Single Event Transients in 250 nm Bulk CMOS Technology T2 - Zuverlässigkeit und Entwurf, 9. ITG/GMM/GI-Fachtagung vom 18.-20. September 2017 in Cottbus Y1 - 2017 SN - 978-3-8007-4444-2 SP - 90 EP - 96 PB - Berlin CY - VDE Verlag ER - TY - CHAP A1 - Maharatna, Koushik A1 - Troya Chinchilla, Alfonso Luis A1 - Krstic, Milos A1 - Grass, Eckhard A1 - Jagdhold, Ulrich T1 - A CORDIC Like Processor for Computation of Arctangent and Absolute Magnitude of a Vector Y1 - 2004 ER - TY - GEN A1 - Perez-Bosch Quesada, Emilio A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Rizzi, Tommaso A1 - Wen, Jianan A1 - Ulbricht, Markus A1 - Krstic, Milos A1 - Wenger, Christian A1 - Perez, Eduardo T1 - Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing T2 - IEEE Transactions on Electron Devices N2 - Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of 8x8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices’ nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems. KW - RRAM KW - Vector Matrix Multiplication KW - variability Y1 - 2023 U6 - https://doi.org/10.1109/TED.2023.3244509 SN - 0018-9383 VL - 70 IS - 4 SP - 2009 EP - 2014 ER - TY - CHAP A1 - Simevski, Aleksandar A1 - Kraemer, Rolf A1 - Krstic, Milos T1 - Low-Complexity Integrated Circuit Aging Monitor Y1 - 2011 ER - TY - CHAP A1 - Schrape, Oliver A1 - Krstic, Milos A1 - Philipp, Gunnar A1 - Winkler, Frank T1 - A Digital Design Flow for Differential ECL High Speed Applications Y1 - 2011 ER - TY - CHAP A1 - Krstic, Milos A1 - Fan, X. A1 - Grass, Eckhard A1 - Strano, A. A1 - Bertozzi, Davide A1 - Heer, Ch. A1 - Sanders, B. A1 - Benini, L. A1 - Kakooe, M. R. T1 - Moonrake Chip - GALS Demonstrator in 40 nm CMOS Technology Y1 - 2011 ER - TY - CHAP A1 - Fan, X. A1 - Krstic, Milos A1 - Wolf, Ch. A1 - Grass, Eckhard T1 - GALS Design for On-Chip Ground Bounce Suppression Y1 - 2011 ER -