TY - CHAP A1 - Zeidler, Steffen A1 - Ehrig, Marcus A1 - Krstic, Milos A1 - Augustin, Michael A1 - Wolf, Christoph A1 - Kraemer, Rolf T1 - Ultra Low Cost Asynchronous Handshake Checker Y1 - 2009 ER - TY - GEN A1 - Krstic, Milos A1 - Fan, X. A1 - Grass, Eckhard A1 - Gürkaynak, F. T1 - GALS for Bursty Data Transfer Based on the Clock Coupling Y1 - 2009 ER - TY - CHAP A1 - Krstic, Milos A1 - Piz, M. A1 - Ehrig, Marcus A1 - Grass, Eckhard T1 - OFDM Datapath Baseband Processor for 1 Gbps Datarate Y1 - 2008 ER - TY - PAT A1 - Fan, X. A1 - Krstic, Milos A1 - Grass, Eckhard T1 - Aussetzbarer Taktgenerator Y1 - 2008 ER - TY - PAT A1 - Krstic, Milos A1 - Grass, Eckhard T1 - GALS-Schaltung mit arbitriertem eingangs- und ausgangsseitigem Taktantrieb Y1 - 2007 ER - TY - CHAP A1 - Krstic, Milos A1 - Grass, Eckhard A1 - Stahl, C. T1 - Request-Driven GALS Technique for Wireless Communication System Y1 - 2005 ER - TY - CHAP A1 - Krstic, Milos A1 - Grass, Eckhard T1 - BIST Testing for GALS Systems Y1 - 2005 ER - TY - CHAP A1 - Krstic, Milos A1 - Grass, Eckhard T1 - GALSification of IEEE 802.11a Baseband Processor Y1 - 2004 ER - TY - CHAP A1 - Maharatna, Koushik A1 - Troya Chinchilla, Alfonso Luis A1 - Banerjee, S. A1 - Grass, Eckhard A1 - Krstic, Milos T1 - A 16-Bit CORDIC Rotator for High-Speed Wireless LAN Y1 - 2004 ER - TY - CHAP A1 - Krstic, Milos A1 - Grass, Eckhard T1 - GALS Baseband Processor for WLAN Y1 - 2004 ER - TY - CHAP A1 - Stahl, C. A1 - Reisig, W. A1 - Krstic, Milos T1 - Hazard Detection in GALS Wrapper: A Case Study Y1 - 2005 ER - TY - JOUR A1 - Maharatna, Koushik A1 - Banerjee, S. A1 - Grass, Eckhard A1 - Krstic, Milos A1 - Troya Chinchilla, Alfonso Luis T1 - Modified Virtually Scaling Free Adaptive CORDIC Rotator Algorithm and Architecture Y1 - 2005 ER - TY - CHAP A1 - Wolf, Christoph A1 - Zeidler, Steffen A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Overview on ATE Test and Debugging Methods for Asynchronous Circuits Y1 - 2011 ER - TY - CHAP A1 - Simevski, Aleksandar A1 - Schleisiek, Klaus A1 - Petrovic, Vladimir A1 - Beller, Norbert A1 - Skoncej, Patryk A1 - Schoof, Gunther A1 - Krstic, Milos T1 - Implementation of a Real Time Unit for Satellite Applications T2 - 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 20-22 April 2016, Kosice, Slovakia Y1 - 2016 SN - 978-1-5090-2467-4 SP - 180 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Babic, Milan A1 - Zeidler, Steffen A1 - Krstic, Milos T1 - GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated Circuits T2 - 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2016), 8-11 May, Porto Alegre, Brazil, 2016 Y1 - 2016 SN - 978-1-4673-9007-1 SP - 67 EP - 74 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Babic, Milan A1 - Krstic, Milos T1 - A Coarse Model for Estimation of Switching Noise Coupling in Lightly Doped Substrates T2 - 18th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Belgrade, Serbia, 2015 Y1 - 2015 SN - 978-1-4799-6780-3 SN - 978-1-4799-6779-7 SP - 217 EP - 222 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Babic, Milan A1 - Fan, Xin A1 - Krstic, Milos T1 - Frequency-Domain Modeling of Ground Bounce and Substrate Noise for Synchronous and GALS Systems T2 - 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 1-4 Sept. Salvador, Brazil 2015 Y1 - 2015 SN - 978-1-4673-9419-2 SP - 126 EP - 132 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Babic, Milan A1 - Krstic, Milos T1 - GALS Methodology for Substrate Noise Reduction in BiCMOS Technologies T2 - Proceedings, Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN), Tallinn, Estonia, 2015 Y1 - 2015 UR - http://www.median-project.eu/wp-content/uploads/MEDIAN-Finale-s2-3.pdf ER - TY - GEN A1 - Andjelkovic, Marko A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Study of the Operation and SET Robustness of a CMOS Pulse Stretching Circuit T2 - Microelectronics Reliability Y1 - 2018 U6 - https://doi.org/10.1016/j.microrel.2017.12.022 SN - 0026-2714 SN - 1872-941X VL - 82 SP - 100 EP - 112 ER - TY - GEN A1 - Segabinazzi Ferreira, Raphael A1 - George, Nevin A1 - Chen, Junchao A1 - Hübner, Michael A1 - Krstic, Milos A1 - Nolte, Jörg A1 - Vierhaus, Heinrich Theodor T1 - Configurable Fault Tolerant Circuits and System Level Integration for Self-Awareness T2 - Proceedings of the Work in Progress Session held in connection with SEAA 2019, the 45th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2019, the 22nd EUROMICRO Conference on Digital System Design N2 - Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on- line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system. Y1 - 2019 SN - 978-3-902457-54-7 U6 - https://doi.org/10.26127/BTUOpen-5050 PB - SEA-Publications CY - Kallithea, Chalkidiki (Greece) ER -