TY - GEN A1 - Fritscher, Markus A1 - Uhlmann, Max A1 - Ostrovskyy, Philip A1 - Reiser, Daniel A1 - Chen, Junchao A1 - Schubert, Andreas A1 - Schulze, Carsten A1 - Kahmen, Gerhard A1 - Fey, Dietmar A1 - Reichenbach, Marc A1 - Krstic, Milos A1 - Wenger, Christian T1 - Area-efficient digital design using RRAM-CMOS standard cells T2 - 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) N2 - Extending the scalability of digital integrated circuits through novel device concepts is an attractive option. Among these concepts, resistive random access memory (RRAM) devices allow fast and nonvolatile operation. However, building large memristive systems is still challenging since large analog circuits have to be designed and integrated. In this paper, we propose a novel solution - the implementation of digital standard cells by the means of RRAM devices. While this methodology is universal, with applications ranging from few-device-circuits to large macroblocks, we demonstrate it for a 2T2R-cell. The benefits of using RRAM devices are demonstrated by implementing a NAND standard cell merely consuming the area of two transistors. This cell is about 25 % smaller than the equivalent CMOS NAND in the same technology. We use these cells to implement a half adder, beating the area of the equivalent CMOS implementation using more sophisticates gates by 15 %. Lastly, we fully integrate this novel standard cell into a digital standard cell library and perform a synthesis and layout of a RISC-V CPU core. KW - RRAM Y1 - 2024 SN - 979-8-3503-5411-9 SN - 979-8-3503-5412-6 U6 - https://doi.org/10.1109/ISVLSI61997.2024.00026 SN - 2159-3477 VL - 18 SP - 81 EP - 87 PB - IEEE ER - TY - GEN A1 - Vinuesa, Guillermo A1 - Garcia, Hector A1 - Duenas, Salvador A1 - Castan, Helena A1 - Iñiguez de la Torre, Ignacio A1 - Gonzalez, Tomas A1 - Dorai Swamy Reddy, Keerthi A1 - Uhlmann, Max A1 - Wenger, Christian A1 - Perez, Eduardo T1 - Effect of the temperature on the performance and dynamic behavior of HfO2-Based Rram Devices T2 - ECS Meeting Abstracts N2 - Over the past decades, the demand for semiconductor memory devices has been steadily increasing, and is currently experiencing an unprecedented boost due to the development and expansion of artificial intelligence. Among emerging high-density non-volatile memories, resistive random-access memory (RRAM) is one of the best recourses for all kind of applications, such as neuromorphic computing or hardware security [1]. Although many materials have been evaluated for RRAM development, some of them with excellent results, HfO2 is one of the established materials in CMOS domain due to its compatibility with standard materials and processes [2]. The main goal of this work is to study the switching capability and stability of HfO2-based RRAMs, as well as to explore their ability in the field of analogue applications, by analyzing the evolution of the resistance states that allow multilevel control. Indeed, analogue operation is a key point for achieving electronic neural synapses in neuromorphic systems, with synaptic weight information encoded in the different resistance states. This research has been carried out over a wide temperature range, between 40 and 340 K, as we are interested in testing the extent to which performance is maintained or modified, with a view to designing neuromorphic circuits that are also suitable in the low-temperature realm. We aim to prove that these simple, fast, high integration density structures can also be used in circuits designed for specific applications, such as aerospace systems. The RRAM devices studied in this work are TiN/Ti/8 nm-HfO2/TiN metal-insulator-metal (MIM) capacitors. Dielectric layers were atomic layer deposited (ALD). It has been demonstrated that the Ti coat in the top electrode acts as a scavenger that absorbs oxygen atoms from the HfO2 layer, and facilitates the creation of conductive filaments of oxygen vacancies [3]. In fact, the oxygen reservoir capability of Ti is well known, as it is able to attract and release oxygen atoms from or to the HfO2 layer during the RRAM operation [4]. The clustering of vacancies extends through the entire thickness of the oxide and, after an electroformig step, it joins the upper and lower electrodes and the device reaches the low resistance state (LRS). By applying adequate electrical signals, the filaments can be partially dissolved, which brings the device into the high-resistance state (HRS), with lower current values. The set process brings the device to the LRS state, while the reset one brings it to the HRS. The dependence of electrical conductivity on external applied electrical excitation allows triggering the device between the both states in a non-volatile manner [5]. The experimental equipment used consisted of a Keithley 4200-SCS semiconductor parameter analyzer and a Lake Shore cryogenic probe station. Fig.1 shows current-voltage cycles measured at different temperatures; the averages values at each temperature, both in logarithmic and linear scale, are also shown. The functional window increases as temperature decreases. The evolutions of set and reset voltage values with temperature are depicted in Fig.2, whereas the current values (measured at 0.1 V) corresponding to the LRS and HRS can be seen in Fig.3. LRS resistance decreases as temperature increases, in agreement with semiconductor behaviour, probably due to a hopping conduction mechanism. Both set and reset voltages decrease as temperature increases; the reset process is smoother at high temperatures. The reduction in reset voltage variability as temperature increases is very notable. Finally, Fig. 4 shows a picture of the transient behaviour; in the right panel of the same figure, the amplitudes of the current transients in the reset state have been included in the external loop. To sum up, the resistive switching phenomena is studied in a wide temperature range. The LRS shows semiconducting behavior with temperature, most likely related to a hopping conduction mechanism. Switching voltages decrease as temperature increases, with a notable reduction in reset voltage variability. An excellent control of intermediate resistance state is shown through current transients at several voltages in the reset process. REFERENCES [1] M. Asif et al., Materials Today Electronics 1, 100004 (2022). [2] S. Slesazeck et al., Nanotechnology 30, 352003 (2019). [3] Z. Fang et al., IEEE Electron Device Letters 35, 9, 912-914 (2014). [4] H. Y. Lee et al., IEEE Electron Device Letters 31, 1, 44-46 (2010). [5] D. J. Wouters et al., Proceedings of the IEEE 103, 8, 1274-1288 (2015). Figure 1 KW - RRAM Y1 - 2024 U6 - https://doi.org/10.1149/MA2024-01211297mtgabs SN - 2151-2043 VL - MA2024-01 IS - 21 SP - 1297 EP - 1297 PB - The Electrochemical Society ER - TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Perez, Eduardo A1 - Uhlmann, Max A1 - Fritscher, Markus A1 - KrishneGowda, Karthik A1 - Ulbricht, Markus A1 - Wenger, Christian A1 - Krstic, Milos T1 - Towards reliable and energy-efficient RRAM based discrete fourier transform accelerator T2 - 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) N2 - The Discrete Fourier Transform (DFT) holds a prominent place in the field of signal processing. The development of DFT accelerators in edge devices requires high energy efficiency due to the limited battery capacity. In this context, emerging devices such as resistive RAM (RRAM) provide a promising solution. They enable the design of high-density crossbar arrays and facilitate massively parallel and in situ computations within memory. However, the reliability and performance of the RRAM-based systems are compromised by the device non-idealities, especially when executing DFT computations that demand high precision. In this paper, we propose a novel adaptive variability-aware crossbar mapping scheme to address the computational errors caused by the device variability. To quantitatively assess the impact of variability in a communication scenario, we implemented an end-to-end simulation framework integrating the modulation and demodulation schemes. When combining the presented mapping scheme with an optimized architecture to compute DFT and inverse DFT(IDFT), compared to the state-of-the-art architecture, our simulation results demonstrate energy and area savings of up to 57 % and 18 %, respectively. Meanwhile, the DFT matrix mapping error is reduced by 83% compared to conventional mapping. In a case study involving 16-quadrature amplitude modulation (QAM), with the optimized architecture prioritizing energy efficiency, we observed a bit error rate (BER) reduction from 1.6e-2 to 7.3e-5. As for the conventional architecture, the BER is optimized from 2.9e-3 to zero. KW - RRAM Y1 - 2024 SN - 978-3-9819263-8-5 SN - 979-8-3503-4860-6 U6 - https://doi.org/10.23919/DATE58400.2024.10546709 SN - 1558-1101 SP - 1 EP - 6 PB - IEEE ER - TY - GEN A1 - Uhlmann, Max A1 - Rizzi, Tommaso A1 - Wen, Jianan A1 - Pérez-Bosch Quesada, Emilio A1 - Al Beattie, Bakr A1 - Ochs, Karlheinz A1 - Pérez, Eduardo A1 - Ostrovskyy, Philip A1 - Carta, Corrado A1 - Wenger, Christian A1 - Kahmen, Gerhard T1 - LUT-based RRAM model for neural accelerator circuit simulation T2 - Proceedings of the 18th ACM International Symposium on Nanoscale Architectures N2 - Neural hardware accelerators have been proven to be energy-efficient when used to solve tasks which can be mapped into an artificial neural network (ANN) structure. Resistive random-access memories (RRAMs) are currently under investigation together with several different memristive devices as promising technologies to build such accelerators combined together with complementary metal-oxide semiconductor (CMOS)-technologies in integrated circuits (ICs). While many research groups are actively developing sophisticated physical-based representations to better understand the underlying phenomena characterizing these devices, not much work has been dedicated to exploit the trade-off between simulation time and accuracy in the definition of low computational demanding models suitable to be used at many abstraction layers. Indeed, the design of complex mixed-signal systems as a neural hardware accelerators requires frequent interaction between the application- and the circuit-level that can be enabled only with the support of accurate and fast-simulating devices’ models. In this work, we propose a solution to fill the aforementioned gap with a lookup table (LUT)-based Verilog-A model of IHP’s 1-transistor-1-RRAM (1T1R) cell. In addition, the implementation challenges of conveying the communication between the abstract ANN simulation and the circuital analysis are tackled with a design flow for resistive neural hardware accelerators that features a custom Python wrapper. As a demonstration of the proposed design flow and 1T1R model, an ANN for the MNIST handwritten digit recognition task is assessed with the last layer verified in circuit simulation. The obtained recognition confidence intervals show a considerable discrepancy between the purely application-level PyTorch simulation and the proposed design flow which spans across the abstraction layers down to the circuital analysis. KW - RRAM KW - Neural network Y1 - 2023 U6 - https://doi.org/10.1145/3611315.3633273 SP - 1 EP - 6 PB - ACM CY - New York, NY, USA ER - TY - GEN A1 - Uhlmann, Max A1 - Pérez-Bosch Quesada, Emilio A1 - Fritscher, Markus A1 - Pérez, Eduardo A1 - Schubert, Markus Andreas A1 - Reichenbach, Marc A1 - Ostrovskyy, Philip A1 - Wenger, Christian A1 - Kahmen, Gerhard T1 - One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing T2 - 21st IEEE Interregional NEWCAS Conference (NEWCAS) N2 - The use of resistive random-access memory (RRAM) for in-memory computing (IMC) architectures has significantly improved the energy-efficiency of artificial neural networks (ANN) over the past years. Current RRAM-technologies are physically limited to a defined unambiguously distinguishable number of stable states and a maximum resistive value and are compatible with present complementary metal-oxide semiconductor (CMOS)-technologies. In this work, we improved the accuracy of current ANN models by using increased weight resolutions of memristive devices, combining two or more in-series RRAM cells, integrated in the back end of line (BEOL) of the CMOS process. Based on system level simulations, 1T2R devices were fabricated in IHP's 130nm SiGe:BiCMOS technology node, demonstrating an increased number of states. We achieved an increase in weight resolution from 3 bit in ITIR cells to 6.5 bit in our 1T2R cell. The experimental data of 1T2R devices gives indications for the performance and energy-efficiency improvement in ITNR arrays for ANN applications. KW - RRAM KW - In-Memory Computing Y1 - 2023 SN - 979-8-3503-0024-6 SN - 979-8-3503-0025-3 U6 - https://doi.org/10.1109/NEWCAS57931.2023.10198073 SN - 2474-9672 SN - 2472-467X PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Perez-Bosch Quesada, Emilio A1 - Rizzi, Tommaso A1 - Gupta, Aditya A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Schubert, Andreas A1 - Pechmann, Stefan A1 - Jia, Ruolan A1 - Uhlmann, Max A1 - Hagelauer, Amelie A1 - Wenger, Christian A1 - Pérez, Eduardo T1 - Multi-Level Programming on Radiation-Hard 1T1R Memristive Devices for In-Memory Computing T2 - 14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023 N2 - This work presents a quasi-static electrical characterization of 1-transistor-1-resistor memristive structures designed following hardness-by-design techniques integrated in the CMOS fabrication process to assure multi-level capabilities in harsh radiation environments. Modulating the gate voltage of the enclosed layout transistor connected in series with the memristive device, it was possible to achieve excellent switching capabilities from a single high resistance state to a total of eight different low resistance states (more than 3 bits). Thus, the fabricated devices are suitable for their integration in larger in-memory computing systems and in multi-level memory applications. Index Terms—radiation-hard, hardness-by-design, memristive devices, Enclosed Layout Transistor, in-memory computing KW - RRAM Y1 - 2023 SN - 979-8-3503-0240-0 U6 - https://doi.org/10.1109/CDE58627.2023.10339525 PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Fritscher, Markus A1 - Uhlmann, Max A1 - Ostrovskyy, Philip A1 - Reiser, Daniel A1 - Chen, Junchao A1 - Wen, Jianan A1 - Schulze, Carsten A1 - Kahmen, Gerhard A1 - Fey, Dietmar A1 - Reichenbach, Marc A1 - Krstic, Milos A1 - Wenger, Christian ED - Wenger, Christian T1 - RISC-V CPU design using RRAM-CMOS standard cells T2 - IEEE transactions on very large scale integration (VLSI) systems N2 - The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely, creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks, we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors, this enables us to construct a nand standard cell, which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS nand gate. We illustrate achievable area savings with a half-adder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates. KW - RRAM KW - Logic gates Y1 - 2025 UR - https://ieeexplore.ieee.org/document/10960690 U6 - https://doi.org/10.1109/TVLSI.2025.3554476 SN - 1063-8210 SP - 1 EP - 9 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York ER - TY - GEN A1 - Uhlmann, Max A1 - Rizzi, Tommaso A1 - Wen, Jianan A1 - Quesada, Emilio Pérez-Bosch A1 - Beattie, Bakr Al A1 - Ochs, Karlheinz A1 - Pérez, Eduardo A1 - Ostrovskyy, Philip A1 - Carta, Corrado A1 - Wenger, Christian A1 - Kahmen, Gerhard T1 - End-to-end design flow for resistive neural accelerators T2 - IEEE transactions on computer-aided design of integrated circuits and systems N2 - Neural hardware accelerators have demonstrated notable energy efficiency in tackling tasks, which can be adapted to artificial neural network (ANN) structures. Research is currently directed towards leveraging resistive random-access memories (RRAMs) among various memristive devices. In conjunction with complementary metal-oxide semiconductor (CMOS) technologies within integrated circuits (ICs), RRAM devices are used to build such neural accelerators. In this study, we present a neural accelerator hardware design and verification flow, which uses a lookup table (LUT)-based Verilog-A model of IHP’s one-transistor-one-RRAM (1T1R) cell. In particular, we address the challenges of interfacing between abstract ANN simulations and circuit analysis by including a tailored Python wrapper into the design process for resistive neural hardware accelerators. To demonstrate our concept, the efficacy of the proposed design flow, we evaluate an ANN for the MNIST handwritten digit recognition task, as well as for the CIFAR-10 image recognition task, with the last layer verified through circuit simulation. Additionally, we implement different versions of a 1T1R model, based on quasi-static measurement data, providing insights on the effect of conductance level spacing and device-to-device variability. The circuit simulations tackle both schematic and physical layout assessment. The resulting recognition accuracies exhibit significant differences between the purely application-level PyTorch simulation and our proposed design flow, highlighting the relevance of circuit-level validation for the design of neural hardware accelerators. KW - RRAM Y1 - 2025 U6 - https://doi.org/10.1109/TCAD.2025.3597237 SN - 0278-0070 SN - 1937-4151 SP - 1 EP - 5 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York ER - TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Uhlmann, Max A1 - Perez, Eduardo A1 - Wenger, Christian A1 - Krstic, Milos T1 - ReFFT : an energy-efficient RRAM-based FFT accelerator T2 - IEEE transactions on computer-aided design of integrated circuits and systems N2 - The fast Fourier transform (FFT) is a highly efficient algorithm for computing the discrete Fourier transform (DFT). It is widely employed in various applications, including digital communication, image processing, and signal analysis. Recently, in-memory computing architectures based on emerging technologies, such as resistive RAM (RRAM), have demonstrated promising performance with low hardware cost for data-intensive applications. However, directly mapping FFT onto RRAM crossbars is challenging because the algorithm relies on many small, sequential butterfly operations, while cross-bars are optimized for large-scale, highly parallel vector–matrix multiplications (VMMs). In this paper, we introduce ReFFT, a system architecture that reformulates FFT computations for efficient execution on RRAM crossbars. ReFFT combines the reduced computational complexity of FFT with the parallel VMM capability of RRAM. We incorporate measured device data into our framework to analyze the effect of variability and develop an adaptive mapping scheme that improves twiddle-factor programming accuracy, leading to a 9.9 dB peak signal-to-noise ratio (PSNR) improvement for a 256-point FFT. Compared with prior RRAM-based DFT designs, ReFFT achieves up to 4.6× and 19.5× higher energy efficiency for 256- and 2048-point FFTs, respectively. The system is further validated in digital communication and satellite image compression tasks. KW - RRAM KW - Accelerator Y1 - 2025 U6 - https://doi.org/10.1109/TCAD.2025.3627146 SN - 0278-0070 SP - 1 EP - 14 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Perez, Eduardo A1 - Maldonado, David A1 - Pechmann, Stefan A1 - Reddy, Keerthi Dorai Swamy A1 - Uhlmann, Max A1 - Hagelauer, Amelie A1 - Roldan, Juan Bautista A1 - Wenger, Christian T1 - Impact of the series resistance on switching characteristics of 1T1R HfO₂-based RRAM devices T2 - 2025 15th Spanish Conference on Electron Devices (CDE) N2 - This study investigates the influence of the series resistance (RS) on the switching characteristics of 1-transistor-1-resistor (1T1R) RRAM devices based on HfO2 and Al:HfO₂ dielectrics. Intrinsic RS values were extracted from I-V characteristics measured over 50 Reset-Set cycles at various gate voltages (VG) by using a numerical transformation method. Results reveal the contribution of the transistor’s resistance to the overall RS. A linear relationship between RS values and Set transition voltages (VTS) was found, with larger RS values amplifying the variability in switching parameters. Comparative analysis of cumulative distribution functions (CDFs) highlights differences between technologies, showing lower VTS values as well as lower sensitivity to RS for Al:HfO₂-based devices. These findings underscore the critical role of RS in modeling and optimizing the performance of RRAM devices for reliable operation. KW - RRAM KW - Memristive device Y1 - 2025 SN - 979-8-3315-9618-7 U6 - https://doi.org/10.1109/CDE66381.2025.11038868 SP - 1 EP - 4 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - Piscataway, NJ ER -