TY - CHAP A1 - Ulbricht, Markus A1 - Schölzel, Mario A1 - Koal, Tobias A1 - Vierhaus, Heinrich Theodor T1 - A New Hierarchical Built-In Test with On-Chip Diagnosis for VLIW Processors T2 - IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS 2011), Cottbus, Germany, 13 - 15 April 2011 N2 - Tagungsbeitrag DDECS 2011, Cottbus KW - Prozessoren KW - Test KW - Zuverlässigkeit Y1 - 2011 UR - www.computer.org SN - 978-1-4244-9755-3 N1 - IEEE Computer Society SP - 143 EP - 146 ER - TY - CHAP A1 - Ulbricht, Markus A1 - Schölzel, Mario A1 - Koal, Tobias A1 - Vierhaus, Heinrich Theodor T1 - A New Hiararchical Built-In SElf Test with On-Chip Diagnosis for VLIW Processors N2 - Tagungsbeitrag 23. ITG-Tagung "Test und Zuverlässigeit von Schaltungen und Systemen", Passau, 2011 KW - Prozessoren KW - Test KW - Zuverlässigkeit Y1 - 2011 N1 - BTU ER - TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Perez, Eduardo A1 - Ulbricht, Markus A1 - Wenger, Christian A1 - Krstic, Milos T1 - Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages T2 - 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) N2 - RRAM technology is a promising candidate for implementing efficient AI accelerators with extensive multiply-accumulate operations. By scaling RRAM devices to the synaptic crossbar array, the computations can be realized in situ, avoiding frequent weights transfer between the processing units and memory. Besides, as the computations are conducted in the analog domain with high flexibility, applying multilevel input voltages to the RRAM devices with multilevel conductance states enhances the computational efficiency further. However, several non-idealities existing in emerging RRAM technology may degrade the reliability of the system. In this paper, we measured and investigated the impact of read disturb on RRAM devices with different input voltages, which incurs conductance drifts and introduces errors. The measured data are deployed to simulate the RRAM based AI inference engines with multilevel states. KW - RRAM KW - Multilevel switching KW - AI accelarator Y1 - 2022 SN - 978-1-6654-5938-9 SN - 978-1-6654-5937-2 U6 - https://doi.org/10.1109/DFT56152.2022.9962345 SN - 2765-933X SP - 1 EP - 6 ER - TY - CHAP A1 - Koal, Tobias A1 - Ulbricht, Markus A1 - Engelke, Piet A1 - Vierhaus, Heinrich Theodor T1 - Kombinierte On-Line-Fehlerkompensation und Selbstreparatur für Logik-Baugruppen T2 - Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, 25. GI/GMM/ITG-Workshop, 24. bis 26. Februar 2013, Dresden Y1 - 2013 PB - Fraunhofer-Institut CY - Dresden ER - TY - CHAP A1 - Koal, Tobias A1 - Ulbricht, Markus A1 - Vierhaus, Heinrich Theodor ED - Raik, Jaan T1 - Combining On-Line Fault Detection and Logic Self Repair T2 - IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS 2012), Tallin, Estonia, 18 - 20 April 2012 Y1 - 2012 SN - 978-1-4673-1185-4 SP - 288 EP - 293 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Koal, Tobias A1 - Ulbricht, Markus A1 - Engelke, Piet A1 - Vierhaus, Heinrich Theodor T1 - Selbstreparatur für Logik-Baugruppen mit erweiterten Fähigkeiten für die Kompensation von Fertigungsfehlern und Frühausfällen T2 - Dresdner Arbeitstagung für Schaltungs- und Systementwurf (DASS), Dresden, Mai 2012, Tagungsband Y1 - 2012 SN - 978-3-8396-0404-5 PB - Fraunhofer IIS, Institutsteil EAS [u.a.] CY - Dresden ER - TY - CHAP A1 - Koal, Tobias A1 - Ulbricht, Markus A1 - Vierhaus, Heinrich Theodor T1 - Virtual TMR Schemes Combining Fault Tolerance and Self Repair T2 - 16th IEEE International Euromicro Conference on Digital System Design, DSD 2013, 4-6 Sep 2013, Santander, Spain Y1 - 2013 SN - 978-0-7695-5074-9 SP - 235 EP - 242 PB - IEEE ER - TY - CHAP A1 - Ulbricht, Markus A1 - Koal, Tobias A1 - Vierhaus, Heinrich Theodor T1 - Activity Migration in M-of-N-Systems by Means of Loading-Balancing T2 - 15th Euromicro Conference on Digital Systems Design (DSD), September 2012 Y1 - 2012 SN - 978-1-4673-2498-4 SP - 258 EP - 263 PB - IEEE CY - Piscataway ER - TY - CHAP A1 - Koal, Tobias A1 - Ulbricht, Markus A1 - Engelke, Piet A1 - Vierhaus, Heinrich Theodor ED - Drechsler, Rolf T1 - Logic Self Repair Architecture with Self Test Capabilities T2 - Zuverlässigkeit und Entwurf, 6. GMM/GI/ITG-Fachtagung vom 25. bis 27. September 2012 in Bremen Y1 - 2012 SN - 978-3-8007-3445-0 PB - VDE-Verl. CY - Berlin [u.a.] ER - TY - CHAP A1 - Koal, Tobias A1 - Ulbricht, Markus A1 - Engelke, Piet A1 - Vierhaus, Heinrich Theodor ED - Dietrich, Manfred T1 - On-Line-Test, Fehlerkorrektur znd Selbstreparatur mit Time-Shared TMR T2 - Tagungsband Dresdner Arbeitstagung für Schaltungs- und Systementwurf (DASS), April 2013 Y1 - 2013 SN - 978-3-8396-0545-5 PB - Fraunhofer-Verl. CY - Stuttgart ER - TY - CHAP A1 - Koal, Tobias A1 - Ulbricht, Markus A1 - Engelke, Piet A1 - Vierhaus, Heinrich Theodor ED - Sekanina, Lukas T1 - On the Feasibility of Combining On-Line-Test and Self Repair for Logic Circuits T2 - 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2013), Karlovny Vary, April 2013 Y1 - 2013 SN - 978-1-4673-6135-4 PB - IEEE Computer Society ER - TY - GEN A1 - Perez-Bosch Quesada, Emilio A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Rizzi, Tommaso A1 - Wen, Jianan A1 - Ulbricht, Markus A1 - Krstic, Milos A1 - Wenger, Christian A1 - Perez, Eduardo T1 - Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing T2 - IEEE Transactions on Electron Devices N2 - Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of 8x8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices’ nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems. KW - RRAM KW - Vector Matrix Multiplication KW - variability Y1 - 2023 U6 - https://doi.org/10.1109/TED.2023.3244509 SN - 0018-9383 VL - 70 IS - 4 SP - 2009 EP - 2014 ER - TY - GEN A1 - Mishurova, Tatjana A1 - Sydow, Benjamin A1 - Thiede, Tobias A1 - Sizova, Irina A1 - Ulbricht, Alexander A1 - Bambach, Markus A1 - Bruno, Giovanni T1 - Residual Stress and Microstructure of a Ti-6Al-4V Wire Arc Additive Manufacturing Hybrid Demonstrator T2 - Metals Y1 - 2020 U6 - https://doi.org/10.3390/met10060701 SN - 2075-4701 VL - 6 IS - 10 ER -