TY - GEN A1 - Medeiros, Thiarles S. A1 - Berned, Gustavo P. A1 - Navarro, Antoni A1 - Rossi, Fábio D. A1 - Luizelli, Marcelo C. A1 - Brandalero, Marcelo A1 - Hübner, Michael A1 - Beck, Antonio Carlos Schneider A1 - Lorenzon, Arthur F. T1 - Aging-Aware Parallel Execution T2 - IEEE Embedded System Letters Y1 - 2020 U6 - https://doi.org/10.1109/LES.2020.3021854 SN - 1943-0663 VL - 13 (2021) IS - 3 SP - 122 EP - 125 ER - TY - GEN A1 - Hernandez, Hector Gerardo Muñoz A1 - Mahmood, Safdar A1 - Brandalero, Marcelo A1 - Hübner, Michael T1 - A Modular Software Library for Effective High-Level Synthesis of Convolutional Neural Networks T2 - Applied Reconfigurable Computing. Architectures, Tools, and Applications, 16th International Symposium, ARC 2020, Toledo, Spain, April 1–3, 2020, Proceedings Y1 - 2020 SN - 978-3-030-44533-1 SN - 978-3-030-44534-8 U6 - https://doi.org/10.1007/978-3-030-44534-8_16 SN - 0302-9743 SN - 1611-3349 SP - 211 EP - 220 PB - Springer CY - Cham ER - TY - GEN A1 - Brandalero, Marcelo A1 - Hernandez, Hector Gerardo Muñoz A1 - Veleski, Mitko A1 - Al Kadi, Muhammed A1 - Rech, Paolo A1 - Hübner, Michael T1 - Enabling Domain-Specific Architectures with an Open-Source Soft-Core GPGPU T2 - 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), New Orleans, LA, 18-22 May 2020 Y1 - 2020 SN - 978-1-7281-7445-7 SN - 978-1-7281-7457-0 U6 - https://doi.org/10.1109/IPDPSW50202.2020.00015 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Souto, Thiago Dadalt A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider T1 - Predicting performance in multi-core systems with shared reconfigurable accelerators T2 - Journal of Systems Architecture Y1 - 2019 U6 - https://doi.org/10.1016/j.sysarc.2019.07.010 SN - 1383-7621 VL - 98 SP - 201 EP - 213 PB - Elsevier ER - TY - GEN A1 - Brandalero, Marcelo A1 - Shafique, Muhammad A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider T1 - TransRec: Improving Adaptability in Single-ISA Heterogeneous Systems with Transparent and Reconfigurable Acceleration T2 - 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) Y1 - 2019 SN - 978-3-9819263-2-3 SN - 978-3-9819263-3-0 SN - 978-1-7281-0331-0 U6 - https://doi.org/10.23919/DATE.2019.8715121 SN - 1558-1101 SN - 1530-1591 SP - 582 EP - 585 ER - TY - GEN A1 - Cardoso, Douglas Maciel A1 - Tonetto, Rafael Billig A1 - Brandalero, Marcelo A1 - Agostini, Luciano A1 - Nazar, Gabriel L. A1 - Azambuja, José Rodrigo A1 - Beck, Antonio Carlos Schneider T1 - Improving Software-based Techniques for Soft Error Mitigation in OoO Superscalar Processors T2 - 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Y1 - 2019 SN - 978-1-7281-0996-1 SN - 978-1-7281-0997-8 U6 - https://doi.org/10.1109/ICECS46596.2019.8964749 SP - 201 EP - 204 ER - TY - GEN A1 - Korol, Guilherme dos Santos A1 - Jordan, Michael Guilherme A1 - Brandalero, Marcelo A1 - Rutzig, Mateus Beck A1 - Beck, Antonio Carlos Schneider T1 - Power-Aware Phase Oriented Reconfigurable Architecture T2 - 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Y1 - 2019 SN - 978-1-7281-0996-1 SN - 978-1-7281-0997-8 U6 - https://doi.org/10.1109/ICECS46596.2019.8965011 SP - 626 EP - 629 ER - TY - GEN A1 - Korol, Guilherme dos Santos A1 - Jordan, Michael Guilherme A1 - Silva, Raul Silveira A1 - Pereira, Monica Magalhães A1 - Brandalero, Marcelo A1 - Rutzig, Mateus Beck A1 - Beck, Antonio Carlos Schneider T1 - A Runtime Power-Aware Phase Predictor for CGRAs T2 - 2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig) Y1 - 2019 SN - 978-1-7281-1957-1 SN - 978-1-7281-1958-8 U6 - https://doi.org/10.1109/ReConFig48160.2019.8994802 SN - 2640-0472 SN - 2325-6532 SP - 1 EP - 8 ER - TY - GEN A1 - Tonetto, Rafael Billig A1 - Cardoso, Douglas Maciel A1 - Brandalero, Marcelo A1 - Agostini, Luciano A1 - Nazar, Gabriel L. A1 - Azambuja, José Rodrigo A1 - Beck, Antonio Carlos Schneider T1 - A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors T2 - 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC) Y1 - 2019 SN - 978-1-7281-3915-9 SN - 978-1-7281-3916-6 U6 - https://doi.org/10.1109/VLSI-SoC.2019.8920350 SN - 2324-8440 SN - 2324-8432 SP - 287 EP - 292 ER - TY - GEN A1 - Exenberger Becker, Pedro H. A1 - Sartor, Anderson L. A1 - Brandalero, Marcelo A1 - Beck, Antonio Carlos Schneider T1 - BRAM-based function reuse for multi-core architectures in FPGAs T2 - Microprocessors and Microsystems Y1 - 2019 U6 - https://doi.org/10.1016/j.micpro.2018.09.007 SN - 0141-9331 VL - 63 SP - 237 EP - 248 ER -