TY - GEN A1 - Medeiros, Thiarles S. A1 - Berned, Gustavo P. A1 - Navarro, Antoni A1 - Rossi, Fábio D. A1 - Luizelli, Marcelo C. A1 - Brandalero, Marcelo A1 - Hübner, Michael A1 - Beck, Antonio Carlos Schneider A1 - Lorenzon, Arthur F. T1 - Aging-Aware Parallel Execution T2 - IEEE Embedded System Letters Y1 - 2020 U6 - https://doi.org/10.1109/LES.2020.3021854 SN - 1943-0663 VL - 13 (2021) IS - 3 SP - 122 EP - 125 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Beck, Antonio Carlos Schneider T1 - Potential of Using a Reconfigurable System on a Superscalar Core for ILP Improvements T2 - 2014 Brazilian Symposium on Computing Systems Engineering Y1 - 2014 SN - 978-1-4799-8559-3 U6 - https://doi.org/10.1109/SBESC.2014.19 SN - 2324-7894 SN - 2324-7886 SP - 43 EP - 48 ER - TY - GEN A1 - Capella, Fernanda M. A1 - Brandalero, Marcelo A1 - Junior, Jair Fajardo A1 - Beck, Antonio Carlos Schneider A1 - Carro, Luigi T1 - A Multiple-ISA Reconfigurable Architecture T2 - 2013 III Brazilian Symposium on Computing Systems Engineering (SBESC), Dec. 4 2013 to Dec. 8 2013, Niteroi, Rio De Janeiro, Brazil Y1 - 2013 U6 - https://doi.org/10.1109/SBESC.2013.23 VL - 1 SP - 71 EP - 76 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Souto, Thiago Dadalt A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider T1 - Predicting performance in multi-core systems with shared reconfigurable accelerators T2 - Journal of Systems Architecture Y1 - 2019 U6 - https://doi.org/10.1016/j.sysarc.2019.07.010 SN - 1383-7621 VL - 98 SP - 201 EP - 213 PB - Elsevier ER - TY - GEN A1 - Brandalero, Marcelo A1 - Shafique, Muhammad A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider T1 - TransRec: Improving Adaptability in Single-ISA Heterogeneous Systems with Transparent and Reconfigurable Acceleration T2 - 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) Y1 - 2019 SN - 978-3-9819263-2-3 SN - 978-3-9819263-3-0 SN - 978-1-7281-0331-0 U6 - https://doi.org/10.23919/DATE.2019.8715121 SN - 1558-1101 SN - 1530-1591 SP - 582 EP - 585 ER - TY - GEN A1 - Cardoso, Douglas Maciel A1 - Tonetto, Rafael Billig A1 - Brandalero, Marcelo A1 - Agostini, Luciano A1 - Nazar, Gabriel L. A1 - Azambuja, José Rodrigo A1 - Beck, Antonio Carlos Schneider T1 - Improving Software-based Techniques for Soft Error Mitigation in OoO Superscalar Processors T2 - 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Y1 - 2019 SN - 978-1-7281-0996-1 SN - 978-1-7281-0997-8 U6 - https://doi.org/10.1109/ICECS46596.2019.8964749 SP - 201 EP - 204 ER - TY - GEN A1 - Korol, Guilherme dos Santos A1 - Jordan, Michael Guilherme A1 - Brandalero, Marcelo A1 - Rutzig, Mateus Beck A1 - Beck, Antonio Carlos Schneider T1 - Power-Aware Phase Oriented Reconfigurable Architecture T2 - 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Y1 - 2019 SN - 978-1-7281-0996-1 SN - 978-1-7281-0997-8 U6 - https://doi.org/10.1109/ICECS46596.2019.8965011 SP - 626 EP - 629 ER - TY - GEN A1 - Korol, Guilherme dos Santos A1 - Jordan, Michael Guilherme A1 - Silva, Raul Silveira A1 - Pereira, Monica Magalhães A1 - Brandalero, Marcelo A1 - Rutzig, Mateus Beck A1 - Beck, Antonio Carlos Schneider T1 - A Runtime Power-Aware Phase Predictor for CGRAs T2 - 2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig) Y1 - 2019 SN - 978-1-7281-1957-1 SN - 978-1-7281-1958-8 U6 - https://doi.org/10.1109/ReConFig48160.2019.8994802 SN - 2640-0472 SN - 2325-6532 SP - 1 EP - 8 ER - TY - GEN A1 - Tonetto, Rafael Billig A1 - Cardoso, Douglas Maciel A1 - Brandalero, Marcelo A1 - Agostini, Luciano A1 - Nazar, Gabriel L. A1 - Azambuja, José Rodrigo A1 - Beck, Antonio Carlos Schneider T1 - A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors T2 - 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC) Y1 - 2019 SN - 978-1-7281-3915-9 SN - 978-1-7281-3916-6 U6 - https://doi.org/10.1109/VLSI-SoC.2019.8920350 SN - 2324-8440 SN - 2324-8432 SP - 287 EP - 292 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Silveira, Leonardo Almeida da A1 - Souza, Jeckson Dellagostin de A1 - Beck, Antonio Carlos Schneider T1 - Accelerating error-tolerant applications with approximate function reuse T2 - Science of Computer Programming Y1 - 2019 U6 - https://doi.org/10.1016/j.scico.2017.05.003 SN - 0167-6423 VL - 165 SP - 54 EP - 67 ER - TY - GEN A1 - Oliveira, Geraldo Francisco A1 - Gonçalves, Larissa Rozales A1 - Brandalero, Marcelo A1 - Beck, Antonio Carlos Schneider A1 - Carro, Luigi T1 - Employing classification-based algorithms for general-purpose approximate computing T2 - 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) Y1 - 2018 SN - 978-1-5386-4114-9 SN - 978-1-5386-4115-6 U6 - https://doi.org/10.1109/DAC.2018.8465822 SP - 70:1 EP - 70:6 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider A1 - Shafique, Muhammad T1 - Approximate on-the-fly coarse-grained reconfigurable acceleration for general-purpose applications T2 - 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) Y1 - 2018 SN - 978-1-5386-4114-9 SN - 978-1-5386-4115-6 U6 - https://doi.org/10.1109/DAC.2018.8465930 SP - 160:1 EP - 160:6 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Malfatti, Guilherme Meneguzzi A1 - Oliveira, Geraldo Francisco A1 - Silveira, Leonardo Almeida da A1 - Gonçalves, Larissa Rozales A1 - Da Silva, Bruno Castro A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider T1 - Efficient Local Memory Support for Approximate Computing T2 - 2018 VIII Brazilian Symposium on Computing Systems Engineering (SBESC) Y1 - 2018 SN - 978-1-7281-0240-5 SN - 978-1-7281-0241-2 U6 - https://doi.org/10.1109/SBESC.2018.00026 SN - 2324-7894 SN - 2324-7886 SP - 122 EP - 129 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Beck, Antonio Carlos Schneider T1 - A Mechanism for energy-efficient reuse of decoding and scheduling of x86 instruction streams T2 - Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 Y1 - 2017 SN - 978-3-9815370-8-6 SN - 978-3-9815370-9-3 SN - 978-1-5090-5826-6 U6 - https://doi.org/10.23919/DATE.2017.7927223 SN - 1558-1101 SP - 1468 EP - 1473 ER - TY - GEN A1 - Silveira, Leonardo Almeida da A1 - Brandalero, Marcelo A1 - Souza, Jeckson Dellagostin de A1 - Beck, Antonio Carlos Schneider T1 - The Potential of Accelerating Image-Processing Applications by Using Approximate Function Reuse T2 - 2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Y1 - 2016 SN - 978-1-5090-2653-1 SN - 978-1-5090-2654-8 U6 - https://doi.org/10.1109/SBESC.2016.026 SN - 2324-7894 SP - 122 EP - 127 ER - TY - GEN A1 - Capella, Fernanda M. A1 - Brandalero, Marcelo A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider T1 - A multiple-ISA reconfigurable architecture T2 - Special Issue on “Selected papers from the 2013 Brazilian Symposium on Computing Systems Engineering (SBESC 2013)” Y1 - 2016 SN - 0929-5585 SN - 1572-8080 VL - 19 IS - 4 SP - 329 EP - 344 ER - TY - GEN A1 - Hoffmann, Javier Eduardo A1 - Brandalero, Marcelo A1 - Hübner, Michael T1 - TIRUB: A Safety and Energy-Aware Scheduling Algorithm T2 - Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA), 23-25 Sept. 2020, Poznan, Poland Y1 - 2020 SN - 978-83-62065-39-4 SN - 978-83-62065-37-0 U6 - https://doi.org/10.23919/SPA50552.2020.9241280 ER - TY - GEN A1 - Fernandes dos Santos, Fernando A1 - Brandalero, Marcelo A1 - Rech Junior, Rubens Luiz A1 - Hübner, Michael A1 - Rech, Paolo A1 - Sullivan, Michael A1 - Martins Basso, Pedro A1 - Carro, Luigi T1 - Reduced Precision DWC: an Efficient Hardening Strategy for Mixed-Precision Architectures T2 - IEEE Transactions on Computers N2 - Duplication with Comparison (DWC) is an effective software-level solution to improve the reliability of computing devices. However, it introduces significant performance and energy consumption overheads that could render the protected application unsuitable for high-performance computing or real-time safety-critical applications. Modern computing architectures offer the possibility to execute operations in various precisions, and recent NVIDIA GPUs even feature dedicated functional units for computing with programmable accuracy. In this work, we propose Reduced-Precision Duplication with Comparison (RP-DWC) as a means to leverage the available mixed-precision hardware resources to implement software-level fault detection with reduced overheads. We discuss the benefits and challenges associated with RP-DWC and show that the intrinsic difference between the mixed-precision copies allows for the detection of most, but not all, errors. However, as the undetected faults are the ones that fall into the difference between precisions, they are the ones that produce a much smaller impact in the application output. We investigate, through fault injection and beam experiment campaigns, using three microbenchmarks and two real applications on Volta GPUs, RP-DWC impact into fault detection, performance, and energy consumption. We show that RP-DWC achieves an excellent coverage (up to 86%) with minimal overheads (0.1% time and 24% energy consumption overhead). Y1 - 2021 U6 - https://doi.org/10.1109/TC.2021.3058872 SN - 0018-9340 VL - 71(2022) IS - 3 SP - 573 EP - 586 ER - TY - GEN A1 - Hernandez, Hector Gerardo Muñoz A1 - Veleski, Mitko A1 - Brandalero, Marcelo A1 - Hübner, Michael ED - Derrien, Steven ED - Hannig, Frank ED - Diniz, Pedro C. ED - Chillet, Daniel T1 - Accelerating Convolutional Neural Networks in FPGA-based SoCs using a Soft-Core GPU T2 - Applied Reconfigurable Computing. Architectures, Tools, and Applications : 17th International Symposium, ARC 2021, Virtual Event, June 29–30, 2021, Proceedings Y1 - 2021 SN - 978-3-030-79024-0 SN - 978-3-030-79025-7 U6 - https://doi.org/10.1007/978-3-030-79025-7_20 SN - 0302-9743 SN - 1611-3349 SP - 275 EP - 284 PB - Springer CY - Cham ER - TY - GEN A1 - Brandalero, Marcelo A1 - Beck, Antonio Carlos Schneider T1 - Potential analysis of a superscalar core employing a reconfigurable array for improving instruction-level parallelism T2 - Special Issue on “SBESC Embedded Systems 2014” Y1 - 2016 U6 - https://doi.org/10.1007/s10617-016-9174-4 SN - 0929-5585 SN - 1572-8080 VL - 20 IS - 2 SP - 155 EP - 169 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Veleski, Mitko A1 - Muñoz-Hernandez, Hector Gerardo A1 - Ali, Muhammad A1 - Le Jeune, Laurens A1 - Goedemé, Toon A1 - Mentens, Nele A1 - Vandendriessche, Jurgen A1 - Lhoest, Lancelot A1 - Da Silva, Bruno A1 - Touhafi, Abdellah A1 - Goehringer, Diana A1 - Hübner, Michael T1 - Embedded AI Techniques for Industrial Applications T2 - 31st International Conference on Field-Programmable Logic and Applications (FPL), Dresden, Germany, 30 August-3 September 2021 Y1 - 2021 SN - 978-1-6654-3759-2 U6 - https://doi.org/10.1109/FPL53798.2021.00071 SP - 374 EP - 375 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Brandalero, Marcelo A1 - Ali, Muhammad A1 - Le Jeune, Laurens A1 - Muñoz Hernandez, Hector Gerardo A1 - Veleski, Mitko A1 - Silva, Bruno da A1 - Lemeire, Jan A1 - Van Beeck, Kristof A1 - Touhafi, Abdellah A1 - Goedemé, Toon A1 - Mentens, Nele A1 - Göhringer, Diana A1 - Hübner, Michael T1 - AITIA: Embedded AI Techniques for Industrial Applications T2 - International Conference on Omni-Layer Intelligent Systems (COINS), 31 August-2 September 2020, Barcelona, Spain Y1 - 2020 SN - 978-1-7281-6371-0 U6 - https://doi.org/10.1109/COINS49042.2020.9191672 SP - 1 EP - 7 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Giani, Braga A1 - Benevenuti, Fabio A1 - Gonçalves, Marcio M. A1 - Hübner, Michael A1 - Brandalero, Marcelo A1 - Kastensmidt, Fernanda A1 - Azambuja, Jose Rodrigo T1 - Evaluating softcore GPU in SRAM-based FPGA under radiation-induced effects T2 - Microelectronics Reliability Y1 - 2021 U6 - https://doi.org/10.1016/j.microrel.2021.114348 SN - 0026-2714 SN - 1872-941X VL - 126 ER - TY - GEN A1 - Exenberger Becker, Pedro H. A1 - Sartor, Anderson L. A1 - Brandalero, Marcelo A1 - Jost, Tiago Trevisan A1 - Wong, Stephan A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider T1 - A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core Processors in FPGAs T2 - Applied Reconfigurable Computing. Architectures, Tools, and Applications 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings Y1 - 2018 SN - 978-3-319-78889-0 SN - 978-3-319-78890-6 U6 - https://doi.org/10.1007/978-3-319-78890-6_40 SN - 0302-9743 SN - 1611-3349 SP - 499 EP - 510 PB - Springer CY - Cham ER - TY - GEN A1 - Exenberger Becker, Pedro H. A1 - Sartor, Anderson L. A1 - Brandalero, Marcelo A1 - Beck, Antonio Carlos Schneider T1 - BRAM-based function reuse for multi-core architectures in FPGAs T2 - Microprocessors and Microsystems Y1 - 2019 U6 - https://doi.org/10.1016/j.micpro.2018.09.007 SN - 0141-9331 VL - 63 SP - 237 EP - 248 ER - TY - GEN A1 - Fricke, Florian A1 - Brandalero, Marcelo A1 - Liehr, Sascha A1 - Kern, Simon A1 - Meyer, Klas A1 - Kowarik, Stefan A1 - Hierzegger, Robin A1 - Westerdick, Stephan A1 - Maiwald, Michael A1 - Hübner, Michael T1 - Artificial Intelligence for Mass Spectrometry and Nuclear Magnetic Resonance Spectroscopy Using a Novel Data Augmentation Method T2 - IEEE Transactions on Emerging Topics in Computing Y1 - 2022 U6 - https://doi.org/10.1109/TETC.2021.3131371 SN - 2168-6750 VL - 10 IS - 1 SP - 87 EP - 98 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider A1 - Shafique, Muhammad T1 - Multi-Target Adaptive Reconfigurable Acceleration for Low-Power IoT Processing T2 - IEEE Transactions on Computers Y1 - 2020 U6 - https://doi.org/10.1109/TC.2020.2984736 SN - 0018-9340 SN - 1557-9956 ER - TY - GEN A1 - Hernandez, Hector Gerardo Muñoz A1 - Mahmood, Safdar A1 - Brandalero, Marcelo A1 - Hübner, Michael T1 - A Modular Software Library for Effective High-Level Synthesis of Convolutional Neural Networks T2 - Applied Reconfigurable Computing. Architectures, Tools, and Applications, 16th International Symposium, ARC 2020, Toledo, Spain, April 1–3, 2020, Proceedings Y1 - 2020 SN - 978-3-030-44533-1 SN - 978-3-030-44534-8 U6 - https://doi.org/10.1007/978-3-030-44534-8_16 SN - 0302-9743 SN - 1611-3349 SP - 211 EP - 220 PB - Springer CY - Cham ER - TY - GEN A1 - Hoffmann, Javier Eduardo A1 - Mahmood, Safdar A1 - Suawa Fogou, Priscile A1 - George, Nevin A1 - Raha, Solaiman A1 - Safi, Sabur A1 - Schmailzl, Kurt JG A1 - Brandalero, Marcelo A1 - Hübner, Michael T1 - A Survey on Machine Learning Approaches to ECG Processing T2 - 2020 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA), 23-25 Sept. 2020 , Poznan, Poland Y1 - 2020 UR - https://ieeexplore.ieee.org/document/9241283 SN - 978-83-62065-39-4 SN - 978-83-62065-37-0 SN - 978-1-7281-7746-5 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Hernandez, Hector Gerardo Muñoz A1 - Veleski, Mitko A1 - Al Kadi, Muhammed A1 - Rech, Paolo A1 - Hübner, Michael T1 - Enabling Domain-Specific Architectures with an Open-Source Soft-Core GPGPU T2 - 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), New Orleans, LA, 18-22 May 2020 Y1 - 2020 SN - 978-1-7281-7445-7 SN - 978-1-7281-7457-0 U6 - https://doi.org/10.1109/IPDPSW50202.2020.00015 ER - TY - GEN A1 - Silva, Raul A1 - Korol, Guilherme dos Santos A1 - Jordan, Michael Guilherme A1 - Brandalero, Marcelo A1 - Hübner, Michael A1 - Pereira, Monica A1 - Rutzig, Mateus Beck A1 - Beck, Antonio Carlos Schneider T1 - A Management Technique for Concurrent Access to a Reconfigurable Accelerator T2 - 33rd Symposium on Integrated Circuits and Systems Design (SBCCI) Y1 - 2020 SN - 978-1-7281-9625-1 SN - 978-1-7281-9626-8 U6 - https://doi.org/10.1109/SBCCI50935.2020.9189927 ER - TY - GEN A1 - Gonçalves, Marcio M. A1 - Benevenuti, Fabio A1 - Munoz-Hernandez, Hector Gerardo A1 - Brandalero, Marcelo A1 - Hübner, Michael A1 - Kastensmidt, Fernanda A1 - Azambuja, Jose Rodrigo T1 - Investigating Floating-Point Implementations in a Softcore GPU under Radiation-Induced Faults T2 - 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), virtual conference, November 23-25, 2020 Y1 - 2020 SN - 978-1-7281-6044-3 SN - 978-1-7281-6045-0 U6 - https://doi.org/10.1109/ICECS49266.2020.9294939 SP - 1 EP - 4 PB - IEEE CY - Piscataway, NJ ER -