TY - GEN A1 - Schwenger, Lars A1 - Holzinger, Philipp A1 - Fey, Dietmar A1 - Munoz Hernandez, Hector Gerardo A1 - Reichenbach, Marc ED - Orailoglu, Alex ED - Reichenbach, Marc ED - Jung, Matthias T1 - EasyHBM: Simple and Fast HBM Access for FPGAs Using High-Level-Synthesis T2 - Embedded computer systems : architectures, modeling, and simulation : 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, proceedings Y1 - 2022 SN - 978-3-031-15073-9 SN - 978-3-031-15074-6 SP - 43 EP - 60 PB - Springer CY - Cham ER - TY - GEN A1 - Knödtel, Johannes A1 - Rachuj, Sebastian A1 - Reichenbach, Marc T1 - Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the best? T2 - 25th Euromicro Conference on Digital System Design (DSD), 31 August 2022 - 02 September 2022, Maspalomas, Spain Y1 - 2022 U6 - https://doi.org/10.1109/DSD57027.2022.00041 SP - 247 EP - 253 PB - IEEE ER - TY - GEN A1 - Fritscher, Markus A1 - Knödtel, Johannes A1 - Mallah, Maen A1 - Pechmann, Stefan A1 - Perez-Bosch Quesada, Emilio A1 - Rizzi, Tommaso A1 - Wenger, Christian A1 - Reichenbach, Marc T1 - Mitigating the Effects of RRAM Process Variation on the Accuracy of Artifical Neural Networks T2 - Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2021. Lecture Notes in Computer Science N2 - Weight storage is a key challenge in the efficient implementation of artificial neural networks. Novel memory technologies such as RRAM are able to greatly improve density and introduce non-volatility and multibit capabilities to this component of ANN accelerators. The usage of RRAM in this domain comes with downsides, mainly caused by cycle-to-cycle and device-to-device variability leading to erroneous readouts, greatly affecting digital systems. ANNs have the ability to compensate for this by their inherent redundancy and usually exhibit a gradual deterioration in the accuracy of the task at hand. This means, that slight error rates can be acceptable for weight storage in an ANN accelerator. In this work we link device-to-device variability to the accuracy of an ANN for such an accelerator. From this study, we can estimate how strongly a certain net is affected by a certain device parameter variability. This methodology is then used to present three mitigation strategies and to evaluate how they affect the reaction of the network to variability: a) Dropout Layers b) Fault-Aware Training c) Redundancy. These mitigations are then evaluated by their ability to improve accuracy and to lower hardware overhead by providing data for a real-word example. We improved this network’s resilience in such a way that it could tolerate double the variation in one of the device parameters (standard deviation of the oxide thickness can be 0.4 nm instead of 0.2 nm while maintaining sufficient accuracy.) KW - RRAM KW - memristive device KW - neural network Y1 - 2022 SN - 978-3-031-04579-0 SN - 978-3-031-04580-6 U6 - https://doi.org/10.1007/978-3-031-04580-6_27 SN - 0302-9743 SN - 1611-3349 SP - 401 EP - 417 PB - Springer ER - TY - GEN A1 - Pechmann, Stefan A1 - Mai, Timo A1 - Völkel, Matthias A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Perez, Eduardo A1 - Perez-Bosch Quesada, Emilio A1 - Reichenbach, Marc A1 - Wenger, Christian A1 - Hagelauer, Amelie T1 - A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells T2 - Electronics N2 - In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9. KW - RRAM KW - Multilevel switching KW - Programming circuit Y1 - 2021 U6 - https://doi.org/10.3390/electronics10050530 SN - 2079-9292 VL - 10 IS - 5 ER - TY - GEN A1 - Suawa Fogou, Priscile A1 - Meisel, Tenia A1 - Jongmanns, Marcel A1 - Hübner, Michael A1 - Reichenbach, Marc T1 - Modeling and Fault Detection of Brushless Direct Current Motor by Deep Learning Sensor Data Fusion T2 - Sensors Y1 - 2022 U6 - https://doi.org/10.3390/s22093516 SN - 1424-8220 VL - 22 IS - 9 ER - TY - GEN A1 - Schlipf, Jon A1 - Berkmann, Fritz A1 - Yamamoto, Yuji A1 - Reichenbach, Marc A1 - Veleski, Mitko A1 - Kawaguchi, Y. A1 - Mörz, Florian A1 - Tomm, Jens W. A1 - Weißhaupt, David A1 - Fischer, Inga Anita T1 - Robust Si/Ge heterostructure metasurfaces as building blocks for wavelength-selective photodetectors T2 - Applied Physics Letters Y1 - 2023 U6 - https://doi.org/10.1063/5.0134458 SN - 1077-3118 VL - 122 IS - 12 ER - TY - GEN A1 - Reiser, Daniel A1 - Reichenbach, Marc A1 - Rizzi, Tommaso A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Wenger, Christian A1 - Zambelli, Cristian A1 - Bertozzi, Davide T1 - Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations T2 - 21st IEEE Interregional NEWCAS Conference (NEWCAS), 26-28 June 2023, Edinburgh, United Kingdom N2 - In-memory computing with resistive-switching random access memory (RRAM) crossbar arrays has the potential to overcome the major bottlenecks faced by digital hardware for data-heavy workloads such as deep learning. However, RRAM devices are subject to several non-idealities that result in significant inference accuracy drops compared with software baseline accuracy. A critical one is related to the drift of the conductance states appearing immediately at the end of program and verify algorithms that are mandatory for accurate multi-level conductance operation. The support of drift models in state-of-the-art simulation tools of memristive computationin-memory is currently only in the early stage, since they overlook key device- and array-level parameters affecting drift resilience such as the programming algorithm of RRAM cells, the choice of target conductance states and the weight-toconductance mapping scheme. The goal of this paper is to fully expose these parameters to RRAM crossbar designers as a multi-dimensional optimization space of drift resilience. For this purpose, a simulation framework is developed, which comes with the suitable abstractions to propagate the effects of those RRAM crossbar configuration parameters to their ultimate implications over inference performance stability. KW - RRAM Y1 - 2023 SN - 979-8-3503-0024-6 SN - 979-8-3503-0025-3 U6 - https://doi.org/10.1109/NEWCAS57931.2023 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Suawa Fogou, Priscile A1 - Halbinger, Anja A1 - Jongmanns, Marcel A1 - Reichenbach, Marc T1 - Noise-Robust Machine Learning Models for Predictive Maintenance Applications T2 - IEEE Sensors Journal N2 - Predictive maintenance of equipment requires a set of data collected through sensors, from which models will learn behaviors that will allow the automatic detection or prediction of these behaviors. The objective is to anticipate unexpected situations such as sudden equipment stoppages. Industries are noisy environments due to production lines that involve a series of components. As a result, the data will always be obstructed by noise. Noise-robust predictive maintenance models, which include ensemble and deep learning models with and without data fusion, are proposed to enhance the monitoring of industrial equipment. The work reported in this article is based on two components, a milling tool, and a motor, with sound, vibration, and ultrasound data collected in real experiments. Four main tasks were performed, namely the construction of the datasets, the training of the monitoring models without adding artificial noise to the data, the evaluation of the robustness of the previously trained models by injecting several levels of noise into the test data, and the optimization of the models by a proposed noisy training approach. The results show that the models maintain their performances at over 95% accuracy despite adding noise in the test phase. These performances decrease by only 2% at a considerable noise level of 15-dB signal-to-noise ratio (SNR). The noisy training method proved to be an optimal solution for improving the noise robustness and accuracy of convolutional deep learning models, whose performance regression of 2% went from a noise level of 28 to 15 dB like the other models. KW - Accelerometer Y1 - 2023 UR - https://ieeexplore.ieee.org/document/10122864 U6 - https://doi.org/10.1109/JSEN.2023.3273458 SN - 1558-1748 SN - 1530-437X VL - 23 IS - 13 SP - 15081 EP - 15092 ER - TY - GEN A1 - Assafo, Maryam A1 - Lautsch, Martin A1 - Suawa, Priscile Fogou A1 - Jongmanns, Marcel A1 - Hübner, Michael A1 - Reichenbach, Marc A1 - Brockmann, Carsten A1 - Reinhardt, Denis A1 - Langendörfer, Peter T1 - The ForTune Toolbox: Building Solutions for Condition-Based and Predictive Maintenance Focusing on Retrofitting Y1 - 2023 SN - 978-3-8007-6204-0 SN - 978-3-8007-6203-3 N1 - Poster, Tagungsband MikroSystemTechnik Kongress 2023, Dresden, 23. - 25. Oktober 2023 SP - S. 541 PB - VDE Verlag CY - Berlin ER - TY - GEN A1 - Hernandez, Hector Gerardo Muñoz A1 - Fricke, Florian A1 - Al Kadi, Muhammed A1 - Reichenbach, Marc A1 - Hübner, Michael T1 - Edge GPU based on an FPGA Overlay Architecture using PYNQ T2 - 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI). 2022 Y1 - 2022 SN - 978-1-6654-8128-1 SN - 978-1-6654-8129-8 U6 - https://doi.org/10.1109/SBCCI55532.2022.9893229 ER - TY - GEN A1 - Sridhar, Vivek A1 - Shahin, Keyvan A1 - Breuß, Michael A1 - Reichenbach, Marc T1 - The Polynomial Connection between Morphological Dilation and Discrete Convolution T2 - arXiv Y1 - 2023 U6 - https://doi.org/10.48550/arXiv.2305.03018 SP - 1 EP - 11 ER - TY - GEN A1 - Shahin, Keyvan A1 - Rotta, Randolf A1 - Archila, Oscar A1 - Mykytyn, Pavlo A1 - Nattke, Matthias A1 - Reichenbach, Marc A1 - Nolte, Jörg A1 - Natarov, Roman T1 - A Modular Communication Architecture for Adaptive UAV Swarms T2 - 2023 IEEE International Conference on Omni-layer Intelligent Systems (COINS) N2 - Small Unmanned Aerial Vehicles (UAVs) have vast application potential from industrial logistics and disaster monitoring to smart farming, for example, to create maps with Normalized Difference Vegetation Index (NDVI) cameras and AI-based image classification or the precision spot application of fertilizers. Operating multiple UAVs in parallel, including those with different specializations, enables efficient coverage of large areas. While existing research focused mainly on predefined flight formations for swarms or autonomous missions for single UAVs, the focus of this work is on multiple UAVs with individually adaptable missions. We derive communication system requirements from swarm coordination algorithms and present a respective design. The resulting modular architecture enables future research on autonomous adaptive UAV swarms and their use as flying sensor platforms. Y1 - 2023 SN - 979-8-3503-4647-3 SN - 979-8-3503-4648-0 U6 - https://doi.org/10.1109/COINS57856.2023.10189245 PB - IEEE CY - Berlin ER - TY - GEN A1 - Vishwakarma, Abhinav A1 - Fritscher, Markus A1 - Hagelauer, Amelie A1 - Reichenbach, Marc T1 - An RRAM-based building block for reprogrammable non-uniform sampling ADCs T2 - Information Technology : it Y1 - 2023 U6 - https://doi.org/10.1515/itit-2023-0021 SN - 2196-7032 VL - 65 IS - 1-2 SP - 39 EP - 51 ER - TY - GEN A1 - Knödtel, Johannes A1 - Munoz Hernandez, Hector Gerardo A1 - Lehnert, Alexander A1 - Thieu, Gia Bao A1 - Gesper, Sven A1 - Payá-Vayá, Guillermo A1 - Reichenbach, Marc ED - Palumbo, Francesca ED - Keramidas, Georgios ED - Voros, Nikolaos ED - Diniz, Pedro C. T1 - TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs T2 - Applied Reconfigurable Computing. Architectures, Tools, and Applications, 19th International Symposium, ARC 2023, Cottbus, Germany, September 27–29, 2023, Proceedings Y1 - 2023 SN - 978-3-031-42920-0 SN - 978-3-031-42921-7 U6 - https://doi.org/10.1007/978-3-031-42921-7_21 SP - 307 EP - 321 PB - Springer CY - Cham ER - TY - GEN A1 - Fricke, Florian A1 - Scharoba, Stefan A1 - Rachuj, Sebastian A1 - Konopik, Andreas A1 - Kluge, Florian A1 - Hofstetter, Georg A1 - Reichenbach, Marc ED - Orailoglu, Alex ED - Reichenbach, Marc ED - Jung, Matthias T1 - Application Runtime Estimation for AURIX Embedded MCU Using Deep Learning  T2 - Embedded computer systems : architectures, modeling, and simulation : 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, proceedings Y1 - 2022 SN - 978-3-031-15073-9 SN - 978-3-031-15074-6 U6 - https://doi.org/10.1007/978-3-031-15074-6_15 SP - 235 EP - 249 PB - Springer CY - Cham ER - TY - GEN A1 - Pechmann, Stefan A1 - Mai, Timo A1 - Potschka, Julian A1 - Reiser, Daniel A1 - Reichel, Peter A1 - Breiling, Marco A1 - Reichenbach, Marc A1 - Hagelauer, Amelie T1 - A Low-Power RRAM Memory Block for Embedded, Multi-Level Weight and Bias Storage in Artificial Neural Networks T2 - Micromachines Y1 - 2021 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:bvb:29-opus4-174878 SN - 2072-666X VL - 12 IS - 11 ER - TY - GEN A1 - Uhlmann, Max A1 - Pérez-Bosch Quesada, Emilio A1 - Fritscher, Markus A1 - Pérez, Eduardo A1 - Schubert, Markus Andreas A1 - Reichenbach, Marc A1 - Ostrovskyy, Philip A1 - Wenger, Christian A1 - Kahmen, Gerhard T1 - One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing T2 - 21st IEEE Interregional NEWCAS Conference (NEWCAS) N2 - The use of resistive random-access memory (RRAM) for in-memory computing (IMC) architectures has significantly improved the energy-efficiency of artificial neural networks (ANN) over the past years. Current RRAM-technologies are physically limited to a defined unambiguously distinguishable number of stable states and a maximum resistive value and are compatible with present complementary metal-oxide semiconductor (CMOS)-technologies. In this work, we improved the accuracy of current ANN models by using increased weight resolutions of memristive devices, combining two or more in-series RRAM cells, integrated in the back end of line (BEOL) of the CMOS process. Based on system level simulations, 1T2R devices were fabricated in IHP's 130nm SiGe:BiCMOS technology node, demonstrating an increased number of states. We achieved an increase in weight resolution from 3 bit in ITIR cells to 6.5 bit in our 1T2R cell. The experimental data of 1T2R devices gives indications for the performance and energy-efficiency improvement in ITNR arrays for ANN applications. KW - RRAM KW - In-Memory Computing Y1 - 2023 SN - 979-8-3503-0024-6 SN - 979-8-3503-0025-3 U6 - https://doi.org/10.1109/NEWCAS57931.2023.10198073 SN - 2474-9672 SN - 2472-467X PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Mahmood, Safdar A1 - Scharoba, Stefan A1 - Schorlemer, Jonas A1 - Schulz, Christian A1 - Hübner, Michael A1 - Reichenbach, Marc T1 - Detecting Improvised Land-mines using Deep Neural Networks on GPR Image Dataset targeting FPGAs  T2 - IEEE Nordic Circuits and Systems Conference (NORCAS), 25-26 October 2022, Oslo, Norway Y1 - 2022 SN - 979-8-3503-4550-6 SN - 979-8-3503-4551-3 U6 - https://doi.org/10.1109/norcas57515.2022.9934735 SP - 1 EP - 7 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Mahmood, Safdar A1 - Hübner, Michael A1 - Reichenbach, Marc ED - Palumbo, Francesca ED - Keramidas, Georgios ED - Voros, Nikolaos ED - Diniz, Pedro C. T1 - A Design-Space Exploration Framework for Application-Specific Machine Learning Targeting Reconfigurable Computing T2 - Applied Reconfigurable Computing. Architectures, Tools, and Applications, 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023 Y1 - 2023 SN - 978-3-031-42921-7 SN - 978-3-031-42920-0 U6 - https://doi.org/10.1007/978-3-031-42921-7_27 SP - 371 EP - 374 PB - Springer CY - Cham ER -