TY - GEN A1 - Mai, Christian A1 - Marschmeyer, Steffen A1 - Peczek, Anna A1 - Kroh, Aleksandra A1 - Jose, Josmy A1 - Reiter, Sebastian A1 - Fischer, Inga Anita A1 - Wenger, Christian A1 - Mai, Andreas T1 - Integration Aspects of Plasmonic TiN-based Nano-Hole-Arrays on Ge Photodetectorsin a 200mm Wafer CMOS Compatible Silicon Technology T2 - ECS Transactions N2 - In this work we present the progress in regard to the integration of a surface plasmon resonance refractive index sensor into a CMOS compatible 200 mm wafer silicon-based technology. Our approach pursues the combination of germanium photodetectors with metallic nanohole arrays. The paper is focused on the technology development to fabricate large area photodetectors based on a modern design concept. In a first iteration we achieved a leakage current density of 82 mA/cm2 at reverse bias of 0.5 V and a maximum optical responsivity of 0.103 A/W measured with TE polarized light at λ = 1310 nm and a reversed bias of 1 V. For the realization of nanohole arrays we used thin Titanium nitride (TiN) layers deposited by a sputtering process. We were able to produce very homogenous TiN layers with a thickness deviation of around 10 % and RMS of 1.413 nm for 150 nm thick TiN layers. KW - plasmonics KW - nanohole array KW - germanium detector Y1 - 2022 U6 - https://doi.org/10.1149/10904.0035ecst SN - 1938-5862 VL - 109 IS - 4 SP - 35 EP - 46 ER - TY - GEN A1 - Lukosius, Mindaugas A1 - Lippert, Gunther A1 - Dabrowski, Jarek Marek A1 - Kitzmann, Julia A1 - Lisker, Marco A1 - Kulse, Philipp A1 - Krüger, Andreas A1 - Fursenko, Oksana A1 - Costina, Ioan A1 - Trusch, Andreas A1 - Yamamoto, Yuji A1 - Wolff, Andre A1 - Mai, Andreas A1 - Schröder, Thomas T1 - Graphene Synthesis and Processing on Ge Substrates T2 - ECS transactions Y1 - 2016 U6 - https://doi.org/10.1149/07508.0533ecst SN - 1938-6737 SN - 1938-5862 VL - 75 IS - 8 SP - 533 EP - 540 ER - TY - GEN A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Pérez, Eduardo A1 - Lisker, Marco A1 - Schubert, Markus Andreas A1 - Perez-Bosch Quesada, Emilio A1 - Wenger, Christian A1 - Mai, Andreas T1 - Modulating the Filamentary-Based Resistive Switching Properties of HfO2 Memristive Devices by Adding Al2O3 Layers T2 - Electronics : open access journal N2 - The resistive switching properties of HfO2 based 1T-1R memristive devices are electrically modified by adding ultra-thin layers of Al2O3 into the memristive device. Three different types of memristive stacks are fabricated in the 130 nm CMOS technology of IHP. The switching properties of the memristive devices are discussed with respect to forming voltages, low resistance state and high resistance state characteristics and their variabilities. The experimental I–V characteristics of set and reset operations are evaluated by using the quantum point contact model. The properties of the conduction filament in the on and off states of the memristive devices are discussed with respect to the model parameters obtained from the QPC fit. KW - RRAM KW - HfO2 KW - filamentary switching Y1 - 2022 U6 - https://doi.org/10.3390/electronics11101540 SN - 2079-9292 VL - 11 IS - 10 ER - TY - CHAP A1 - Mai, Andreas A1 - Dauderstädt, Ulrike A1 - Pahner, D. A1 - Krellmann, M. A1 - Schmeißer, Dieter A1 - Wagner, M. T1 - In situ determination of laser induced degradation of micro-mirror arrays T2 - International Students and Young Scientists Workshop Photonics and Microsystems, Cottbus, Germany, 8 - 10 June 2011 N2 - The Fraunhofer Institute for Photonic Microsystems (Fraunhofer IPMS) develops spatial light modulators (SLMs) based on arrays of tiltable micro mirrors on a semiconductor chip. Typical applications are pattern generation for deepUV-laser mask writing or structured illumination in microscopy. Development and optimization of such SLMs requires detailed knowledge of the device behaviour under operating conditions. Here, the flatness of each single mirror effects the image resolution and contrast of the generated pattern and is amongst others a characteristic property of SLMs. In this context a surface topography measurement under laser exposure (in situ) was designed. The interferometric setup uses the phase-shift principle and allows a resolution in z-direction in the single-digit nanometer range. During irradiation with UV-laser light at 248 nm (KrF) and energy densities of up to 20 mJ/cm2 the change in single micro-mirrors topography was detected in situ. Measurementswith varying pulse energies were carried out to identify an impacton the device performance. In general, the setup is neither limited to a specific illumination wavelength nor to micro-mirrors as structures under test. KW - micro-mirror arrays KW - laser induced degradation Y1 - 2011 SN - 978-1-4577-1651-5 U6 - https://doi.org/10.1109/STYSW.2011.6155850 SP - 84 EP - 88 PB - IEEE CY - Piscataway, NJ ER - TY - THES A1 - Mai, Andreas T1 - Integration von LDMOS-Transistoren für Hochfrequenzanwendungen in eine 0.13 µm-SiGe:C-BiCMOS Technologie Y1 - 2010 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-opus-20740 ER - TY - GEN A1 - Lukosius, Mindaugas A1 - Dabrowski, Jarek Marek A1 - Lisker, Marco A1 - Kitzmann, Julia A1 - Schulze, Sebastian A1 - Lippert, Gunther A1 - Fursenko, Oksana A1 - Yamamoto, Yuji A1 - Schubert, Markus Andreas A1 - Krause, Hans-Michael A1 - Wolff, Andre A1 - Mai, A. A1 - Schröder, Thomas A1 - Lupina, Grzegorz T1 - Metal-free, CVD Graphene synthesis on 200 mm Ge / Si(001) substrates T2 - ACS Applied Materials and Interfaces Y1 - 2016 U6 - https://doi.org/10.1021/acsami.6b11397 SN - 1944-8244 SN - 1944-8252 VL - 8 IS - 49 SP - 33786 EP - 33793 ER - TY - GEN A1 - Schenk, Harald A1 - Villasmunta, Francesco A1 - Steglich, Patrick A1 - Schrader, Sigurd A1 - Mai, Andreas T1 - Numerical Simulation of Optical Through-Silicon Waveguide for 3D Photonic Interconnections T2 - 2021 International Conference on Numerical Simulation of Optoelectronic Devices (NUSOD) N2 - Optical interconnections are a promising step for-ward to overcome the intrinsic limitations of electrical inter-connections in integrated circuits. In this work, we present a finite element method (FEM) simulation study of a dielectric waveguide etched through the full thickness of a silicon substrate. In particular, it is investigated the effect of the bridge-to-core size ratio on the first two supported modes. Then, the influence of the waveguide sidewalls tapering angle on the three-dimensional beam propagation is studied. Such optical through-silicon waveguide (OTSW), if nonadiabatically tapered can provide effective mode size conversion and favour the coupling of external light sources to photonic integrated circuits. Y1 - 2021 UR - https://ieeexplore.ieee.org/document/9541464 SN - 978-1-6654-1276-6 SN - 978-1-6654-4836-9 U6 - https://doi.org/10.1109/NUSOD52207.2021.9541464 SN - 2158-3242 SN - 2158-3234 PB - IEEE ER - TY - GEN A1 - Lukosius, Mindaugas A1 - Lukose, Rasuolė A1 - Lisker, Marco A1 - Luongo, G. A1 - Elviretti, M. A1 - Mai, Andreas A1 - Wenger, Christian T1 - Graphene Research in 200 mm CMOS Pilot Line T2 - 45th Jubilee International Convention on Information, Communication and Electronic Technology (MIPRO), 2022 N2 - Due to the unique electronic structures, graphene and other 2D Materials are considered as materials which can enable and extend the functionalities and performance in a large variety of applications, among them in microelectronics. At this point, the investigation and preparation of graphene devices in conditions resembling as close as possible the Si technology environment is of highest importance.Towards these goals, this paper focuses on the full spectra of graphene research aspects in 200mm pilot line. We investigated different process module developments such as CMOS compatible growth of high quality graphene on germanium and its growth mechanisms, transfer related challenges on target substrates, patterning, passivation and various concepts of contacting of graphene on a full 200 mm wafers. Finally, we fabricated proof-of-concept test structures e.g. TLM, Hall bars and capacitor structures to prove the feasibility of graphene processing in the pilot line of IHP. KW - Graphene KW - CMOS Y1 - 2022 SN - 978-953-233-103-5 SN - 978-953-233-102-8 SN - 978-1-6654-8434-3 U6 - https://doi.org/10.23919/MIPRO55190.2022.9803362 SN - 2623-8764 SN - 1847-3938 SP - 113 EP - 117 ER - TY - GEN A1 - Villasmunta, Francesco A1 - Steglich, Patrick A1 - Heinrich, Friedhelm A1 - Villringer, Claus A1 - Mai, Andreas A1 - Schrader, Sigurd A1 - Schenk, Harald T1 - Optical Through-Silicon Waveguides for 3D-Chip-Interconnections N2 - Integrated optical interconnections in silicon chips have the potential to replace electrical interconnects between integrated circuits thanks to their high bandwidth and low energy communication promises. A silicon dielectric waveguide can be etched through the full thickness of a silicon substrate providing a monolithically integrated solution for 2.5D and 3D photonic architectures. The optical through-silicon waveguide design presented here is based on Finite Difference Time Domain simulations, while the fabrication takes advantage of the innovative plasma cryo-etching process that provides smooth sidewalls and tapering angle tunability. Such structures can provide effective mode size conversion, therefore favoring the coupling of external light sources to photonic integrated circuits and the stacking of multiple optically interconnected dies. KW - Integrated Optics KW - Micro Optics KW - Optical Information Transmission Y1 - 2023 UR - https://www.dgao-proceedings.de/abstract/abstract_only.php?id=2920 ER - TY - GEN A1 - Dorai Swamy Reddy, Keerthi A1 - Pérez, Eduardo A1 - Baroni, Andrea A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Marschmeyer, Steffen A1 - Fraschke, Mirko A1 - Lisker, Marco A1 - Wenger, Christian A1 - Mai, Andreas T1 - Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance T2 - The European Physical Journal B N2 - Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal–insulator–metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2 dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm HfO2 dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology. KW - RRAM Y1 - 2024 U6 - https://doi.org/10.1140/epjb/s10051-024-00821-1 SN - 1434-6028 VL - 97 PB - Springer Science and Business Media LLC ER - TY - GEN A1 - Villasmunta, Francesco A1 - Steglich, Patrick A1 - Villringer, Claus A1 - Schrader, Sigurd A1 - Schenk, Harald A1 - Mai, Andreas A1 - Regehly, Martin ED - Schröder, Henning ED - Chen, Ray T. T1 - Design, fabrication, and characterization of integrated optical through-silicon waveguides for 3D photonic interconnections T2 - Optical Interconnects XXIV Y1 - 2024 U6 - https://doi.org/10.1117/12.3003146 PB - SPIE ER - TY - GEN A1 - Reiter, Sebastian A1 - Han, Weijia A1 - Mai, Christian A1 - Spirito, Davide A1 - Jose, Josmy A1 - Zöllner, Marvin Hartwig A1 - Fursenko, Oksana A1 - Schubert, Markus Andreas A1 - Stemmler, Ivo A1 - Wenger, Christian A1 - Fischer, Inga Anita T1 - Titanium Nitride Plasmonic Nanohole Arrays for CMOS-compatible integrated refractive index sensing: influence of layer thickness on optical properties T2 - Plasmonics Y1 - 2023 U6 - https://doi.org/10.1007/s11468-023-01810-3 SN - 1557-1963 SP - 1 EP - 13 ER - TY - GEN A1 - Raju, Ashraful Islam A1 - Dubey, Pawan Kumar A1 - Lukose, Rasuole A1 - Wenger, Christian A1 - Mai, Andreas A1 - Lukosius, Mindaugas T1 - Optimized silicon nitride-spaced graphene electro-optic modulator with high efficiency and bandwidth T2 - Optical and quantum electronics N2 - Optical modulators with high modulation efficiency, large operational bandwidth, high-speed and low energy consumption is essential for the advancement of on-chip optical signal processing. To overcome the bandwidth-efficiency trade-off in graphene optical modulators, a buried silicon nitride waveguide-coupled double-layer graphene electro-absorption (EA) optical modulator has been proposed. In the proposed design, silicon nitride layer is also embedded between the two graphene layers as a dielectric spacer to enhance the graphene-light interaction. An extensive simulation has been performed to optimize the dielectric spacing layers between the two graphene for optimal device performance including the waveguide dimensions and optical modes profile. The simulated results show a high modulation efficiency of 1.1 dB/V and a modulation depth of 0.16 dB/µm, corresponding to a 15-dB extinction ratio for a 100 µm device at 1550 nm, with a 30 nm spacer and 12 V driving voltage. The proposed modulator achieves a 14 GHz bandwidth and operates over a 1050 nm broadband operation spectral range. The concurrent presence of high modulation bandwidth and efficiency renders these modulator designs highly viable for on-chip optical communication applications. KW - Graphene KW - Modulator Y1 - 2025 U6 - https://doi.org/10.1007/s11082-025-08310-0 SN - 1572-817X VL - 57 IS - 7 SP - 1 EP - 15 PB - Springer Science and Business Media LLC CY - Dordrecht ER - TY - GEN A1 - Fünning, Tabea A1 - Paul, Martin A1 - Manganelli, Costanza Lucia A1 - Wenger, Christian A1 - Mai, Andreas A1 - Steglich, Patrick T1 - Comparative simulation analysis of photonic ultrasound sensors based on silicon waveguides T2 - Scientific reports N2 - Pressure sensors based on photonic integrated circuits (PIC) offer the prospect of outstanding sensitivities, extreme miniaturization and have the potential for highly scalable production using CMOS compatible processing. PIC-based pressure sensors detect the change in optical properties, i.e. the intensity or phase of the optical carrier wave inside miniaturized waveguide structures. The detection of ultrasound is achieved by engineering the waveguide architecture such that a pressure causes a high change in the effective refractive index of the waveguide. A range of PIC-based pressure sensors have been reported, but a comparison of the sensitivity of the different approaches is not straightforward, since different pressure sensitive waveguide architectures as well as photonic layouts and measurement setups impact the performance. Additionally, the used sensitivity unit is not uniform throughout the different studies, further complicating a comparison. In this work, a detailed simulation study is carried out by finite element modeling of different pressure sensitive waveguide architectures for a consistent comparison. We analyze three different sensor architectures: (A) a free standing membrane located within a tiny air gap above the waveguide, (B) a waveguide located on top of a deflectable membrane as well as (C) a waveguide embedded inside a pressure-sensitive polymer cladding. The mechanical response of the structures and the resulting changes in mode propagation, i.e. the change of the effective refractive index, are analyzed. The waveguide sensitivities in RIU/MPa for different waveguide types (strip, slot) and polarization states (TE, TM) are compared. The results reveal inherent limitations of the different waveguide designs and create a basis for the selection of suitable designs for further ultrasound sensor development. Possibilities for enhancing waveguide sensitivity are identified and discussed. Additionally, we have shown that the studied approaches are extensible to SiN waveguides. KW - Ultrasound sensor Y1 - 2025 U6 - https://doi.org/10.1038/s41598-025-01953-9 SN - 2045-2322 VL - 15 IS - 1 SP - 1 EP - 13 PB - Springer Science and Business Media LLC CY - [London] ER - TY - GEN A1 - Villasmunta, Francesco A1 - Heise, Patrick A1 - Breiter, Manuela A1 - Schrader, Sigurd A1 - Schenk, Harald A1 - Regehly, Martin A1 - Mai, Andreas T1 - Monolithically integrated optical through-silicon waveguides for 3D chip-to-chip photonic interconnects T2 - IEEE journal of selected topics in quantum electronics N2 - The scaling limitations of electrical interconnects are driving the demand for efficient optical chip-to-chip links. We report the first monolithic integration of air-clad optical through-silicon waveguides in silicon, fabricated via Bosch and cryogenic deep reactive-ion etching. Rib, single-bridge, and double-bridge designs with 50 μm cores and up to 150 μm propagation lengths have been evaluated. Cryogenic-etched rib waveguides achieve the highest median transmission (66%, −1.80 dB), compared to Bosch-etched ribs (62%, −2.08 dB). Across all geometries, 3 dB alignment windows range from 9.3 μm to 49.2 μm, with Bosch-etched double-bridge waveguides providing the broadest tolerance. We show that geometric fidelity outweighs sidewall roughness for transmission and alignment in these large-core, multimode optical through-silicon waveguides. This technology provides a scalable, complementary metal-oxide semiconductor-compatible pathway toward 3D photonic interconnects. KW - Optical interconnections KW - Silicon photonics KW - Three-dimensional integrated circuits KW - Through-silicon vias (TSV) Y1 - 2026 U6 - https://doi.org/10.1109/JSTQE.2025.3615001 SN - 1077-260X SN - 1558-4542 VL - 32 IS - 2: 3-D Horizons in Photonics SP - 1 EP - 15 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York, NY ER -