TY - GEN A1 - Mai, Christian A1 - Marschmeyer, Steffen A1 - Peczek, Anna A1 - Kroh, Aleksandra A1 - Jose, Josmy A1 - Reiter, Sebastian A1 - Fischer, Inga Anita A1 - Wenger, Christian A1 - Mai, Andreas T1 - Integration Aspects of Plasmonic TiN-based Nano-Hole-Arrays on Ge Photodetectorsin a 200mm Wafer CMOS Compatible Silicon Technology T2 - ECS Transactions N2 - In this work we present the progress in regard to the integration of a surface plasmon resonance refractive index sensor into a CMOS compatible 200 mm wafer silicon-based technology. Our approach pursues the combination of germanium photodetectors with metallic nanohole arrays. The paper is focused on the technology development to fabricate large area photodetectors based on a modern design concept. In a first iteration we achieved a leakage current density of 82 mA/cm2 at reverse bias of 0.5 V and a maximum optical responsivity of 0.103 A/W measured with TE polarized light at λ = 1310 nm and a reversed bias of 1 V. For the realization of nanohole arrays we used thin Titanium nitride (TiN) layers deposited by a sputtering process. We were able to produce very homogenous TiN layers with a thickness deviation of around 10 % and RMS of 1.413 nm for 150 nm thick TiN layers. KW - plasmonics KW - nanohole array KW - germanium detector Y1 - 2022 U6 - https://doi.org/10.1149/10904.0035ecst SN - 1938-5862 VL - 109 IS - 4 SP - 35 EP - 46 ER - TY - GEN A1 - Lukosius, Mindaugas A1 - Lippert, Gunther A1 - Dabrowski, Jarek Marek A1 - Kitzmann, Julia A1 - Lisker, Marco A1 - Kulse, Philipp A1 - Krüger, Andreas A1 - Fursenko, Oksana A1 - Costina, Ioan A1 - Trusch, Andreas A1 - Yamamoto, Yuji A1 - Wolff, Andre A1 - Mai, Andreas A1 - Schröder, Thomas T1 - Graphene Synthesis and Processing on Ge Substrates T2 - ECS transactions Y1 - 2016 U6 - https://doi.org/10.1149/07508.0533ecst SN - 1938-6737 SN - 1938-5862 VL - 75 IS - 8 SP - 533 EP - 540 ER - TY - GEN A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Perez, Eduardo A1 - Lisker, Marco A1 - Schubert, Markus Andreas A1 - Perez-Bosch Quesada, Emilio A1 - Wenger, Christian A1 - Mai, Andreas T1 - Modulating the Filamentary-Based Resistive Switching Properties of HfO2 Memristive Devices by Adding Al2O3 Layers T2 - Electronics : open access journal N2 - The resistive switching properties of HfO2 based 1T-1R memristive devices are electrically modified by adding ultra-thin layers of Al2O3 into the memristive device. Three different types of memristive stacks are fabricated in the 130 nm CMOS technology of IHP. The switching properties of the memristive devices are discussed with respect to forming voltages, low resistance state and high resistance state characteristics and their variabilities. The experimental I–V characteristics of set and reset operations are evaluated by using the quantum point contact model. The properties of the conduction filament in the on and off states of the memristive devices are discussed with respect to the model parameters obtained from the QPC fit. KW - RRAM KW - HfO2 KW - filamentary switching Y1 - 2022 U6 - https://doi.org/10.3390/electronics11101540 SN - 2079-9292 VL - 11 IS - 10 ER - TY - THES A1 - Mai, Andreas T1 - Integration von LDMOS-Transistoren für Hochfrequenzanwendungen in eine 0.13 µm-SiGe:C-BiCMOS Technologie Y1 - 2010 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-opus-20740 ER - TY - GEN A1 - Lukosius, Mindaugas A1 - Dabrowski, Jarek Marek A1 - Lisker, Marco A1 - Kitzmann, Julia A1 - Schulze, Sebastian A1 - Lippert, Gunther A1 - Fursenko, Oksana A1 - Yamamoto, Yuji A1 - Schubert, Markus Andreas A1 - Krause, Hans-Michael A1 - Wolff, Andre A1 - Mai, A. A1 - Schröder, Thomas A1 - Lupina, Grzegorz T1 - Metal-free, CVD Graphene synthesis on 200 mm Ge / Si(001) substrates T2 - ACS Applied Materials and Interfaces Y1 - 2016 U6 - https://doi.org/10.1021/acsami.6b11397 SN - 1944-8244 SN - 1944-8252 VL - 8 IS - 49 SP - 33786 EP - 33793 ER - TY - CHAP A1 - Mai, Andreas A1 - Dauderstädt, Ulrike A1 - Pahner, D. A1 - Krellmann, M. A1 - Schmeißer, Dieter A1 - Wagner, M. T1 - In situ determination of laser induced degradation of micro-mirror arrays T2 - International Students and Young Scientists Workshop Photonics and Microsystems, Cottbus, Germany, 8 - 10 June 2011 N2 - The Fraunhofer Institute for Photonic Microsystems (Fraunhofer IPMS) develops spatial light modulators (SLMs) based on arrays of tiltable micro mirrors on a semiconductor chip. Typical applications are pattern generation for deepUV-laser mask writing or structured illumination in microscopy. Development and optimization of such SLMs requires detailed knowledge of the device behaviour under operating conditions. Here, the flatness of each single mirror effects the image resolution and contrast of the generated pattern and is amongst others a characteristic property of SLMs. In this context a surface topography measurement under laser exposure (in situ) was designed. The interferometric setup uses the phase-shift principle and allows a resolution in z-direction in the single-digit nanometer range. During irradiation with UV-laser light at 248 nm (KrF) and energy densities of up to 20 mJ/cm2 the change in single micro-mirrors topography was detected in situ. Measurementswith varying pulse energies were carried out to identify an impacton the device performance. In general, the setup is neither limited to a specific illumination wavelength nor to micro-mirrors as structures under test. KW - micro-mirror arrays KW - laser induced degradation Y1 - 2011 SN - 978-1-4577-1651-5 U6 - https://doi.org/10.1109/STYSW.2011.6155850 SP - 84 EP - 88 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Lukosius, Mindaugas A1 - Lukose, Rasuolė A1 - Lisker, Marco A1 - Luongo, G. A1 - Elviretti, M. A1 - Mai, Andreas A1 - Wenger, Christian T1 - Graphene Research in 200 mm CMOS Pilot Line T2 - 45th Jubilee International Convention on Information, Communication and Electronic Technology (MIPRO), 2022 N2 - Due to the unique electronic structures, graphene and other 2D Materials are considered as materials which can enable and extend the functionalities and performance in a large variety of applications, among them in microelectronics. At this point, the investigation and preparation of graphene devices in conditions resembling as close as possible the Si technology environment is of highest importance.Towards these goals, this paper focuses on the full spectra of graphene research aspects in 200mm pilot line. We investigated different process module developments such as CMOS compatible growth of high quality graphene on germanium and its growth mechanisms, transfer related challenges on target substrates, patterning, passivation and various concepts of contacting of graphene on a full 200 mm wafers. Finally, we fabricated proof-of-concept test structures e.g. TLM, Hall bars and capacitor structures to prove the feasibility of graphene processing in the pilot line of IHP. KW - Graphene KW - CMOS Y1 - 2022 SN - 978-953-233-103-5 SN - 978-953-233-102-8 SN - 978-1-6654-8434-3 U6 - https://doi.org/10.23919/MIPRO55190.2022.9803362 SN - 2623-8764 SN - 1847-3938 SP - 113 EP - 117 ER - TY - GEN A1 - Reiter, Sebastian A1 - Han, Weijia A1 - Mai, Christian A1 - Spirito, Davide A1 - Jose, Josmy A1 - Zöllner, Marvin Hartwig A1 - Fursenko, Oksana A1 - Schubert, Markus Andreas A1 - Stemmler, Ivo A1 - Wenger, Christian A1 - Fischer, Inga Anita T1 - Titanium Nitride Plasmonic Nanohole Arrays for CMOS-Compatible Integrated Refractive Index Sensing: Influence of Layer Thickness on Optical Properties T2 - Plasmonics Y1 - 2023 U6 - https://doi.org/10.1007/s11468-023-01810-3 SN - 1557-1963 SP - 1 EP - 13 ER - TY - GEN A1 - Villasmunta, Francesco A1 - Steglich, Patrick A1 - Heinrich, Friedhelm A1 - Villringer, Claus A1 - Mai, Andreas A1 - Schrader, Sigurd A1 - Schenk, Harald T1 - Optical Through-Silicon Waveguides for 3D-Chip-Interconnections N2 - Integrated optical interconnections in silicon chips have the potential to replace electrical interconnects between integrated circuits thanks to their high bandwidth and low energy communication promises. A silicon dielectric waveguide can be etched through the full thickness of a silicon substrate providing a monolithically integrated solution for 2.5D and 3D photonic architectures. The optical through-silicon waveguide design presented here is based on Finite Difference Time Domain simulations, while the fabrication takes advantage of the innovative plasma cryo-etching process that provides smooth sidewalls and tapering angle tunability. Such structures can provide effective mode size conversion, therefore favoring the coupling of external light sources to photonic integrated circuits and the stacking of multiple optically interconnected dies. KW - Integrated Optics KW - Micro Optics KW - Optical Information Transmission Y1 - 2023 UR - https://www.dgao-proceedings.de/abstract/abstract_only.php?id=2920 ER - TY - GEN A1 - Schenk, Harald A1 - Villasmunta, Francesco A1 - Steglich, Patrick A1 - Schrader, Sigurd A1 - Mai, Andreas T1 - Numerical Simulation of Optical Through-Silicon Waveguide for 3D Photonic Interconnections T2 - 2021 International Conference on Numerical Simulation of Optoelectronic Devices (NUSOD) N2 - Optical interconnections are a promising step for-ward to overcome the intrinsic limitations of electrical inter-connections in integrated circuits. In this work, we present a finite element method (FEM) simulation study of a dielectric waveguide etched through the full thickness of a silicon substrate. In particular, it is investigated the effect of the bridge-to-core size ratio on the first two supported modes. Then, the influence of the waveguide sidewalls tapering angle on the three-dimensional beam propagation is studied. Such optical through-silicon waveguide (OTSW), if nonadiabatically tapered can provide effective mode size conversion and favour the coupling of external light sources to photonic integrated circuits. Y1 - 2021 UR - https://ieeexplore.ieee.org/document/9541464 SN - 978-1-6654-1276-6 SN - 978-1-6654-4836-9 U6 - https://doi.org/10.1109/NUSOD52207.2021.9541464 SN - 2158-3242 SN - 2158-3234 PB - IEEE ER -