TY - GEN A1 - Lukosius, Mindaugas A1 - Lukose, Rasuolė A1 - Lisker, Marco A1 - Luongo, G. A1 - Elviretti, M. A1 - Mai, Andreas A1 - Wenger, Christian T1 - Graphene Research in 200 mm CMOS Pilot Line T2 - 45th Jubilee International Convention on Information, Communication and Electronic Technology (MIPRO), 2022 N2 - Due to the unique electronic structures, graphene and other 2D Materials are considered as materials which can enable and extend the functionalities and performance in a large variety of applications, among them in microelectronics. At this point, the investigation and preparation of graphene devices in conditions resembling as close as possible the Si technology environment is of highest importance.Towards these goals, this paper focuses on the full spectra of graphene research aspects in 200mm pilot line. We investigated different process module developments such as CMOS compatible growth of high quality graphene on germanium and its growth mechanisms, transfer related challenges on target substrates, patterning, passivation and various concepts of contacting of graphene on a full 200 mm wafers. Finally, we fabricated proof-of-concept test structures e.g. TLM, Hall bars and capacitor structures to prove the feasibility of graphene processing in the pilot line of IHP. KW - Graphene KW - CMOS Y1 - 2022 SN - 978-953-233-103-5 SN - 978-953-233-102-8 SN - 978-1-6654-8434-3 U6 - https://doi.org/10.23919/MIPRO55190.2022.9803362 SN - 2623-8764 SN - 1847-3938 SP - 113 EP - 117 ER - TY - GEN A1 - Capista, Daniele A1 - Lukose, Rasuole A1 - Majnoon, Farnaz A1 - Lisker, Marco A1 - Wenger, Christian A1 - Lukosius, Mindaugas T1 - Optimization of the metal deposition process for the accurate estimation of Low Metal-Graphene Contact-Resistance T2 - 47th MIPRO ICT and Electronics Convention (MIPRO), 20-24 May 2024, Opatija, Croatia Y1 - 2024 SN - 979-8-3503-8250-1 SN - 979-8-3503-8249-5 U6 - https://doi.org/10.1109/MIPRO60963.2024.10569895 SN - 2623-8764 ER - TY - GEN A1 - Lukosius, Mindaugas A1 - Lukose, Rasuolė A1 - Dubey, P. K. A1 - Raju, A. I. A1 - Capista, Daniele A1 - Lisker, Marco A1 - Mai, A. A1 - Wenger, Christian T1 - Graphene for photonic applications T2 - 2024 47th MIPRO ICT and Electronics Convention (MIPRO) N2 - Integrating graphene into Silicon Complementary Metal-Oxide-Semiconductor (CMOS) technology for photonic applications holds immense promise, but it encounters challenges in establishing large-scale graphene processes. These challenges encompass growth through techniques like Chemical Vapor Deposition (CVD), transfer, encapsulation, and contact formation within a routine 200mm wafer pilot line typically utilized for integrated circuit fabrication. This study is dedicated to exploring various facets of graphene research within a 200 mm pilot line, with a focus on overcoming challenges through the fabrication of proof-of-concept photonic graphene-based devices. The synthesis of graphene targeted epi-Ge(100)/Si(100) substrates, grown within the IHP pilot line, showcasing the potential for high-quality graphene deposition across 200mm wafers. Alternatively, employing different orientations such as (110) has been explored to enhance graphene mobility, achieving a remarkable mobility of 2300 cm 2 /Vs at present. The study systematically investigates graphene quality, thickness, and homogeneity utilizing techniques such as Raman spectroscopy, Atomic Force Microscopy (AFM), and Scanning Electron Microscopy (SEM). Additionally, simulations and fabrication of the graphene ring modulators have been conducted at both the component and device levels, incorporating realistic graphene properties. These results indicate a modulation depth of 1.6 dB/μm and a 3dB bandwidth of 7 GHz, showcasing the potential of graphene-based photonic devices for high-speed communication applications. KW - Graphene Y1 - 2024 SN - 979-8-3503-8250-1 SN - 979-8-3503-8249-5 U6 - https://doi.org/10.1109/MIPRO60963.2024.10569652 SN - 2623-8764 SP - 1614 EP - 1618 PB - IEEE ER - TY - GEN A1 - Akhtar, Fatima A1 - Dabrowski, Jaroslaw A1 - Lukose, Rasuole A1 - Wenger, Christian A1 - Lukosius, Mindaugas T1 - Chemical Vapor Deposition Growth of Graphene on 200 mm Ge (110)/Si Wafers and Ab Initio Analysis of Differences in Growth Mechanisms on Ge (110) and Ge (001) T2 - ACS Applied Materials & Interfaces N2 - For the fabrication of modern graphene devices, uniform growth of high-quality monolayer graphene on wafer scale is important. This work reports on the growth of large-scale graphene on semiconducting 8 inch Ge(110)/Si wafers by chemical vapor deposition and a DFT analysis of the growth process. Good graphene quality is indicated by the small FWHM (32 cm–1) of the Raman 2D band, low intensity ratio of the Raman D and G bands (0.06), and homogeneous SEM images and is confirmed by Hall measurements: high mobility (2700 cm2/Vs) and low sheet resistance (800 Ω/sq). In contrast to Ge(001), Ge(110) does not undergo faceting during the growth. We argue that Ge(001) roughens as a result of vacancy accumulation at pinned steps, easy motion of bonded graphene edges across (107) facets, and low energy cost to expand Ge area by surface vicinals, but on Ge(110), these mechanisms do not work due to different surface geometries and complex reconstruction. KW - Graphene KW - Chemical Vapor Deposition Y1 - 2023 U6 - https://doi.org/10.1021/acsami.3c05860 SN - 1944-8244 VL - 15 IS - 30 SP - 36966 EP - 36974 ER - TY - GEN A1 - Capista, Daniele A1 - Lukose, Rasuole A1 - Majnoon, Farnaz A1 - Lisker, Marco A1 - Wenger, Christian A1 - Lukosius, Mindaugas T1 - Study on the metal -graphene contact resistance achieved with one -dimensional contact architecture T2 - IEEE Nanotechnology Materials and Devices Conference (NMDC 2023), Paestum, Italy, 22-25 October 2023 N2 - Graphene has always been considered as one of the materials with the greatest potential for the realization of improved microelectronic and photonic devices. But to actually reach its full potential in Si CMOS technology, graphene -based devices need to overcome different challenges. They do not only need to have better performances than standard devices, but they also need to be compatible with the production of standard Si based devices. To address the first challenge the main route requires the optimization of the contact resistance, that highly reduces the devices performance, while the second challenges requires the integration of graphene inside the standard production lines used for microelectronic. In this work we used an 8” wafer pilot -line to realize our devices and we studied the behavior of the contact resistance between metal and graphene obtained by one -dimensional contact architecture between the two materials. The contact resistance has been measured by means of Transmission Line Method (TLM) with several contact patterning. KW - Graphene Y1 - 2023 SN - 979-8-3503-3546-0 U6 - https://doi.org/10.1109/NMDC57951.2023.10343775 SP - 118 EP - 119 PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Lukosius, Mindaugas A1 - Lukose, Rasuolė A1 - Lisker, Marco A1 - Dubey, P. K. A1 - Raju, A. I. A1 - Capista, Daniele A1 - Majnoon, Farnaz A1 - Mai, A. A1 - Wenger, Christian T1 - Developments of Graphene devices in 200 mm CMOS pilot line T2 - Proc. Nanotechnology Materials and Devices Conference (NMDC 2023),Paestum, Italy, 22-25 October 2023 N2 - Due to the unique electronic band structure, graphene has opened great potential to extend the functionality of a large variety of devices. Despite the significant progress in the fabrication of various graphene based microelectronic devices, the integration of graphene devices still lack the stability and compatibility with Si-technology processes. Therefore, the investigation and preparation of graphene devices in conditions resembling as close as possible the Si technology environment is of highest importance. This study aims to explore various aspects of graphene research on a 200mm pilot line, with a focus on simulations and fabrication of graphene modulator. To be more precise, it includes design and fabrication of the layouts, necessary mask sets, creation of the flows, fabrication, and measurements of the Gr modulators on 200 mm wafers. KW - Graphene Y1 - 2023 SN - 979-8-3503-3546-0 U6 - https://doi.org/10.1109/NMDC57951.2023.10343569 SP - 505 EP - 506 PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Raju, Ashraful Islam A1 - Dubey, Pawan Kumar A1 - Lukose, Rasuole A1 - Wenger, Christian A1 - Mai, Andreas A1 - Lukosius, Mindaugas T1 - Optimized silicon nitride-spaced graphene electro-optic modulator with high efficiency and bandwidth T2 - Optical and quantum electronics N2 - Optical modulators with high modulation efficiency, large operational bandwidth, high-speed and low energy consumption is essential for the advancement of on-chip optical signal processing. To overcome the bandwidth-efficiency trade-off in graphene optical modulators, a buried silicon nitride waveguide-coupled double-layer graphene electro-absorption (EA) optical modulator has been proposed. In the proposed design, silicon nitride layer is also embedded between the two graphene layers as a dielectric spacer to enhance the graphene-light interaction. An extensive simulation has been performed to optimize the dielectric spacing layers between the two graphene for optimal device performance including the waveguide dimensions and optical modes profile. The simulated results show a high modulation efficiency of 1.1 dB/V and a modulation depth of 0.16 dB/µm, corresponding to a 15-dB extinction ratio for a 100 µm device at 1550 nm, with a 30 nm spacer and 12 V driving voltage. The proposed modulator achieves a 14 GHz bandwidth and operates over a 1050 nm broadband operation spectral range. The concurrent presence of high modulation bandwidth and efficiency renders these modulator designs highly viable for on-chip optical communication applications. KW - Graphene KW - Modulator Y1 - 2025 U6 - https://doi.org/10.1007/s11082-025-08310-0 SN - 1572-817X VL - 57 IS - 7 SP - 1 EP - 15 PB - Springer Science and Business Media LLC CY - Dordrecht ER - TY - GEN A1 - Dubey, Pawan Kumar A1 - Raju, Ashraful Islam A1 - Lukose, Rasuole A1 - Wenger, Christian A1 - Lukosius, Mindaugas T1 - Optimizing graphene ring modulators : a comparative study of straight, bent, and racetrack geometries T2 - Nanomaterials N2 - Graphene-based micro-ring modulators are promising candidates for next-generation optical interconnects, offering compact footprints, broadband operation, and CMOS compatibility. However, most demonstrations to date have relied on conventional straight bus coupling geometries, which limit design flexibility and require extremely small coupling gaps to reach critical coupling. This work presents a comprehensive comparative analysis of straight, bent, and racetrack bus geometries in graphene-on-silicon nitride (Si₃N₄) micro-ring modulators operating near 1.31 µm. Based on finite-difference time-domain simulation results, a proposed racetrack-based modulator structure demonstrates that extending the coupling region enables critical coupling at larger gaps—up to 300 nm—while preserving high modulation efficiency. With only 6–12% graphene coverage, this geometry achieves extinction ratios of up to 28 dB and supports electrical bandwidths approaching 90 GHz. Findings from this work highlight a new co-design framework for coupling geometry and graphene coverage, offering a pathway to high-speed and high-modulation-depth graphene photonic modulators suitable for scalable integration in next-generation photonic interconnects devices. KW - Graphene Y1 - 2025 U6 - https://doi.org/10.3390/nano15151158 SN - 2079-4991 VL - 15 IS - 15 SP - 1 EP - 17 PB - MDPI AG CY - Basel ER -