TY - GEN A1 - Capellini, Giovanni A1 - Kozłowski, Grzegorz A1 - Yamamoto, Yuji A1 - Lisker, Marco A1 - Tillack, Bernd A1 - Ghrib, A. A1 - Kersauson, M. de A1 - El Kurdi, M. A1 - Boucaud, P. A1 - Schroeder, Thomas T1 - Tensile strained Ge layers obtained via Si-CMOS compatible approach T2 - Journal of Applied Physics Y1 - 2013 VL - 113 IS - 1 SP - 013513-1 EP - 013513-6 ER - TY - GEN A1 - Lukosius, Mindaugas A1 - Lippert, Gunther A1 - Dabrowski, Jarek Marek A1 - Kitzmann, Julia A1 - Lisker, Marco A1 - Kulse, Philipp A1 - Krüger, Andreas A1 - Fursenko, Oksana A1 - Costina, Ioan A1 - Trusch, Andreas A1 - Yamamoto, Yuji A1 - Wolff, Andre A1 - Mai, Andreas A1 - Schröder, Thomas T1 - Graphene Synthesis and Processing on Ge Substrates T2 - ECS transactions Y1 - 2016 U6 - https://doi.org/10.1149/07508.0533ecst SN - 1938-6737 SN - 1938-5862 VL - 75 IS - 8 SP - 533 EP - 540 ER - TY - GEN A1 - Lukosius, Mindaugas A1 - Dabrowski, Jarek Marek A1 - Lisker, Marco A1 - Kitzmann, Julia A1 - Schulze, Sebastian A1 - Lippert, Gunther A1 - Fursenko, Oksana A1 - Yamamoto, Yuji A1 - Schubert, Markus Andreas A1 - Krause, Hans-Michael A1 - Wolff, Andre A1 - Mai, A. A1 - Schröder, Thomas A1 - Lupina, Grzegorz T1 - Metal-free, CVD Graphene synthesis on 200 mm Ge / Si(001) substrates T2 - ACS Applied Materials and Interfaces Y1 - 2016 U6 - https://doi.org/10.1021/acsami.6b11397 SN - 1944-8244 SN - 1944-8252 VL - 8 IS - 49 SP - 33786 EP - 33793 ER - TY - GEN A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Pérez, Eduardo A1 - Lisker, Marco A1 - Schubert, Markus Andreas A1 - Perez-Bosch Quesada, Emilio A1 - Wenger, Christian A1 - Mai, Andreas T1 - Modulating the Filamentary-Based Resistive Switching Properties of HfO2 Memristive Devices by Adding Al2O3 Layers T2 - Electronics : open access journal N2 - The resistive switching properties of HfO2 based 1T-1R memristive devices are electrically modified by adding ultra-thin layers of Al2O3 into the memristive device. Three different types of memristive stacks are fabricated in the 130 nm CMOS technology of IHP. The switching properties of the memristive devices are discussed with respect to forming voltages, low resistance state and high resistance state characteristics and their variabilities. The experimental I–V characteristics of set and reset operations are evaluated by using the quantum point contact model. The properties of the conduction filament in the on and off states of the memristive devices are discussed with respect to the model parameters obtained from the QPC fit. KW - RRAM KW - HfO2 KW - filamentary switching Y1 - 2022 U6 - https://doi.org/10.3390/electronics11101540 SN - 2079-9292 VL - 11 IS - 10 ER - TY - GEN A1 - Lukosius, Mindaugas A1 - Lukose, Rasuolė A1 - Lisker, Marco A1 - Luongo, G. A1 - Elviretti, M. A1 - Mai, Andreas A1 - Wenger, Christian T1 - Graphene Research in 200 mm CMOS Pilot Line T2 - 45th Jubilee International Convention on Information, Communication and Electronic Technology (MIPRO), 2022 N2 - Due to the unique electronic structures, graphene and other 2D Materials are considered as materials which can enable and extend the functionalities and performance in a large variety of applications, among them in microelectronics. At this point, the investigation and preparation of graphene devices in conditions resembling as close as possible the Si technology environment is of highest importance.Towards these goals, this paper focuses on the full spectra of graphene research aspects in 200mm pilot line. We investigated different process module developments such as CMOS compatible growth of high quality graphene on germanium and its growth mechanisms, transfer related challenges on target substrates, patterning, passivation and various concepts of contacting of graphene on a full 200 mm wafers. Finally, we fabricated proof-of-concept test structures e.g. TLM, Hall bars and capacitor structures to prove the feasibility of graphene processing in the pilot line of IHP. KW - Graphene KW - CMOS Y1 - 2022 SN - 978-953-233-103-5 SN - 978-953-233-102-8 SN - 978-1-6654-8434-3 U6 - https://doi.org/10.23919/MIPRO55190.2022.9803362 SN - 2623-8764 SN - 1847-3938 SP - 113 EP - 117 ER - TY - GEN A1 - Dorai Swamy Reddy, Keerthi A1 - Pérez, Eduardo A1 - Baroni, Andrea A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Marschmeyer, Steffen A1 - Fraschke, Mirko A1 - Lisker, Marco A1 - Wenger, Christian A1 - Mai, Andreas T1 - Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance T2 - The European Physical Journal B N2 - Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal–insulator–metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2 dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm HfO2 dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology. KW - RRAM Y1 - 2024 U6 - https://doi.org/10.1140/epjb/s10051-024-00821-1 SN - 1434-6028 VL - 97 PB - Springer Science and Business Media LLC ER - TY - GEN A1 - Capista, Daniele A1 - Lukose, Rasuole A1 - Majnoon, Farnaz A1 - Lisker, Marco A1 - Wenger, Christian A1 - Lukosius, Mindaugas T1 - Optimization of the metal deposition process for the accurate estimation of Low Metal-Graphene Contact-Resistance T2 - 47th MIPRO ICT and Electronics Convention (MIPRO), 20-24 May 2024, Opatija, Croatia Y1 - 2024 SN - 979-8-3503-8250-1 SN - 979-8-3503-8249-5 U6 - https://doi.org/10.1109/MIPRO60963.2024.10569895 SN - 2623-8764 ER - TY - GEN A1 - Lukosius, Mindaugas A1 - Lukose, Rasuolė A1 - Dubey, P. K. A1 - Raju, A. I. A1 - Capista, Daniele A1 - Lisker, Marco A1 - Mai, A. A1 - Wenger, Christian T1 - Graphene for photonic applications T2 - 2024 47th MIPRO ICT and Electronics Convention (MIPRO) N2 - Integrating graphene into Silicon Complementary Metal-Oxide-Semiconductor (CMOS) technology for photonic applications holds immense promise, but it encounters challenges in establishing large-scale graphene processes. These challenges encompass growth through techniques like Chemical Vapor Deposition (CVD), transfer, encapsulation, and contact formation within a routine 200mm wafer pilot line typically utilized for integrated circuit fabrication. This study is dedicated to exploring various facets of graphene research within a 200 mm pilot line, with a focus on overcoming challenges through the fabrication of proof-of-concept photonic graphene-based devices. The synthesis of graphene targeted epi-Ge(100)/Si(100) substrates, grown within the IHP pilot line, showcasing the potential for high-quality graphene deposition across 200mm wafers. Alternatively, employing different orientations such as (110) has been explored to enhance graphene mobility, achieving a remarkable mobility of 2300 cm 2 /Vs at present. The study systematically investigates graphene quality, thickness, and homogeneity utilizing techniques such as Raman spectroscopy, Atomic Force Microscopy (AFM), and Scanning Electron Microscopy (SEM). Additionally, simulations and fabrication of the graphene ring modulators have been conducted at both the component and device levels, incorporating realistic graphene properties. These results indicate a modulation depth of 1.6 dB/μm and a 3dB bandwidth of 7 GHz, showcasing the potential of graphene-based photonic devices for high-speed communication applications. KW - Graphene Y1 - 2024 SN - 979-8-3503-8250-1 SN - 979-8-3503-8249-5 U6 - https://doi.org/10.1109/MIPRO60963.2024.10569652 SN - 2623-8764 SP - 1614 EP - 1618 PB - IEEE ER - TY - GEN A1 - Tetzner, Henriette A1 - Seifert, W. A1 - Skibitzki, Oliver A1 - Yamamoto, Yuji A1 - Lisker, Marco A1 - Mirza, M. M. A1 - Fischer, Inga Anita A1 - Paul, Douglas J. A1 - De Seta, Monica A1 - Capellini, Giovanni T1 - Unintentional p-type conductivity in intrinsic Ge-rich SiGe/Ge heterostructures grown on Si(001) T2 - Applied Physics Letter Y1 - 2023 U6 - https://doi.org/10.1063/5.0152962 SN - 1077-3118 VL - 122 IS - 24 ER - TY - GEN A1 - Capista, Daniele A1 - Lukose, Rasuole A1 - Majnoon, Farnaz A1 - Lisker, Marco A1 - Wenger, Christian A1 - Lukosius, Mindaugas T1 - Study on the metal -graphene contact resistance achieved with one -dimensional contact architecture T2 - IEEE Nanotechnology Materials and Devices Conference (NMDC 2023), Paestum, Italy, 22-25 October 2023 N2 - Graphene has always been considered as one of the materials with the greatest potential for the realization of improved microelectronic and photonic devices. But to actually reach its full potential in Si CMOS technology, graphene -based devices need to overcome different challenges. They do not only need to have better performances than standard devices, but they also need to be compatible with the production of standard Si based devices. To address the first challenge the main route requires the optimization of the contact resistance, that highly reduces the devices performance, while the second challenges requires the integration of graphene inside the standard production lines used for microelectronic. In this work we used an 8” wafer pilot -line to realize our devices and we studied the behavior of the contact resistance between metal and graphene obtained by one -dimensional contact architecture between the two materials. The contact resistance has been measured by means of Transmission Line Method (TLM) with several contact patterning. KW - Graphene Y1 - 2023 SN - 979-8-3503-3546-0 U6 - https://doi.org/10.1109/NMDC57951.2023.10343775 SP - 118 EP - 119 PB - Institute of Electrical and Electronics Engineers (IEEE) ER -